A collection of synthesisable RTL designs, SoC subsystems, arithmetic hardware, and interactive educational presentations covering modern hardware engineering topics. Browse the interactive decks below, or follow the repo links for the underlying source code.
Origins at UC Berkeley · Base ISAs (RV32I/64I/32E/128I) · Standard extensions (M·A·F·D·C·V·B·K·H) · Privilege model · Vectors · Vendors · Interactive instruction encoder & CPU stepper
History of Arm (Acorn → ARM1 → Armv9) · Cortex-M family (M0 – M85) · Armv6-M / v7-M / v8-M · Programmer's model · NVIC · MPU · DSP / FPU / Helium · CoreSight debug · Low-power · TrustZone — with interactive core & ISA-version pickers
History of AMBA (1996 → 2024) · AHB & APB · AXI deep dive (channels, bursts, IDs, QoS, Lite & Stream) · ACE & ACE-Lite coherency · CHI scalable coherency (CMN-600/650/700) · Future (CHI-C2C, UCIe chiplets, CXL, MPAM, RME / CCA, AI accelerators) — SystemVerilog snippets + minimal-hardware patterns throughout
History & family (ARM11 → A9 → A15 + big.LITTLE → A53/A57 AArch64 pivot → A76/A78 → Cortex-X1 → X925) · Armv8-A / v9-A architecture & EL0-EL3 · Memory system (VMSA, caches, ordering, LSE atomics) · NEON / SVE / SVE2 / SME vectors · Security (TrustZone-A · PAC · BTI · MTE · RME / CCA) · OoO microarchitecture & DynamIQ — with interactive core and EL pickers
History & product lines (N1 / V1 / E1 / N2 / V2 / N3 / V3) · Server microarchitecture & RAS · CMN-600/650/700/S3 mesh · SBSA + SystemReady + platform contract · Ecosystem — AWS Graviton 1-4, Ampere Altra / AmpereOne, NVIDIA Grace-Hopper, Microsoft Cobalt, Alibaba Yitian, SiPearl Rhea, Fujitsu A64FX — with interactive Neoverse-silicon picker
GIC (v2/v3/v4, GIC-400/500/600/700, SPI/PPI/SGI/LPI, ITS, vGIC) · SMMU (v2/v3, SMMU-600/700, stream tables, ATS/PASID/PRI, IORT) · DynamIQ Shared Unit (DSU-110/120/120AE, shared L3, CHI egress) · MPAM + CoreSight (Linux resctrl, DAP, ETM, ITM, STM, CTI, TRBE)
Packaging · NoC · Memory · SerDes · ML accelerators · Security · CXL · Power & thermal · Clocks · FPGAs · Finance
Field solvers (FDTD, FEM, MoM) · SPICE and switching simulators · Event-driven and cycle-based RTL, emulation, FPGA prototypes · Architecture models from roofline to cycle-level · System DES, queueing and Monte Carlo · Virtual platforms · Stiffness, co-simulation, V&V · An interactive four-solver demo · Links into every simulation deck here
Icarus · Verilator · Vivado xsim · Questa Starter · slang — a construct-by-construct support matrix, real error messages and workarounds, and an interactive “which simulator runs my testbench?” picker
CKKS as a hardware workload · Anatomy of bootstrapping · A SimPy accelerator model with a live in-browser simulator · Optical NTT engines: precision, conversion & power · Design-space results: SRAM, key traffic, NTT-bound vs memory-bound
Rust for simulation engineers · A bit-exact Rust/PyO3 port of a SimPy simulator · C++ models in SystemC TLM-2.0 · Modelling DRAM and HBM · A cocotb/Verilator verification bridge · Testing frameworks · Jenkins · Jira and metrics · Specifications and test plans · PyTorch/ONNX front ends · Performance analysis · Measurement tools and methods · Power, performance and area · An accelerator model in SimPy, end to end
Transmission lines · return paths · materials & causality · vias · differential pairs · crosstalk · a four-deck jitter section · a four-deck power-integrity section · timing · measurement · COM — seventeen decks, every number computed by a model
S-parameters · pulse response · CTLE / FFE / DFE · noise budget · PAM4 & FEC · chiplets · serial memory & CXL — one 28 GBd backplane channel worked end to end
PWM (voltage-mode, current-mode) · PFM · Hysteretic · COT · Digital control · GaN — with interactive waveform and efficiency graphics
GF(2) and GF(2n) arithmetic · Irreducible polynomials · Applications in CRC, LFSR, AES, error-correcting codes
Deep-dive on the MMUL — the kernel of every AI accelerator. History (Kung 1978/82 → TPU → V100 → Blackwell) · 4 dataflows (OS / WS / IS / row-stationary, DPT) · Transformer mapping (Q/K/V/FFN GEMMs) · Number formats (FP32 → FP4, MXFP, NVFP4) · Real systems (TPU/Trillium, H100/B200, Cerebras WSE-3, Groq, Dojo, Trainium, ANE, AMX, SME, Sohu, Tenstorrent) · Memory hierarchy & caches · Power, thermals & PDN — with 4 parameterised SV implementations, Python golden model, and 258 passing tests
Interactive web app: the matrix hardware under the models, in 9 animated chapters · Why systolic (the memory wall) · Weight-, output- and input-stationary cycle by cycle · Skew, fill and drain · Tiling big GEMMs with double-buffered weights · Inside a PE (a bfloat16/FP16/INT8 MAC pipeline) · The TPU and a torus all-reduce · Row-stationary and tensor cores · An ONNX graph lowered onto the array — every frame from a cycle-accurate model checked against the author's SystemVerilog array and MAC unit in Verilator
Light as interconnect and as compute. Silicon Photonics Fundamentals is the foundation: the device physics the other series link to instead of re-explaining.
Waveguides, couplers and WDM, with a mode solver in the browser · Mach–Zehnder and ring modulators, germanium photodiodes, with a modulator explorer · Lasers, packaging and the energy-per-bit budget, with a link-budget explorer. The device glossary the data-centre and AI-processing series build on
Pluggable transceivers to linear-drive optics, with a module-power explorer · Co-packaged optics and optical I/O · Optical circuit switching: Google's optical spine and TPU v4 · Optical networks for AI clusters, with a transceiver-count calculator. Device physics linked from Silicon Photonics Fundamentals
A map of optical computing, with an MZI-mesh error explorer · Optical matrix multiply: precision, conversions and an energy-per-MAC model · Where optics could win, and the limits, with a win map · The public landscape, every company claim attributed and labelled, with a claim checker
Fourier optics for engineers: the 4f system, ENOB, conversion energy · Where transforms appear in LLM inference: an Amdahl analysis · Optical prefill pools, simulated: heterogeneous pools, break-even points and compute in transit for the KV hand-off, with a live in-browser simulator
Transforms in training workloads: the backward pass, weight-masked and data-by-data products, and a training-step Amdahl explorer · Optical backpropagation and in-situ training, with a live three-trainer demo · Optical engines in a training cluster: mask rewrites per step, layer-major scheduling and DeMo
The follow-on to Fourier Optics for Inference: computing on LLM training and inference traffic as it crosses a link, including a photonic link module (arXiv:2608.21536), its operations-per-byte budget, frequency-domain gradient compression and the KV hand-off
Top-level SoC integrating CPU, crossbar, MMU, cache, DMA and IOMMU into a unified bus-connected system with PLIC, SRAM and peripheral bridge
In-order 5-stage pipeline · Full forwarding · 2-way set-associative caches · AXI4-Lite bus · Branch prediction · M and C extensions
Parameterised N×M AXI4 crossbar — round-robin arbitration, ID-based response routing, error slave, independent read/write paths
Sv32 MMU with fully-associative TLB, hardware page-table walker, permission checking and SFENCE.VMA support
4-way set-associative L2 cache with MESI coherence, write-back policy, snoop interface and AXI4 bus interface
4-channel DMA with scatter-gather, AXI4 master interface and per-channel interrupts
I/O address translation for DMA isolation — IOTLB, device-context cache and fault handling
Platform-Level Interrupt Controller — priority-based arbitration, configurable enable / threshold, claim/complete handshake
Restoring · Non-restoring · SRT radix-2/4 · Newton-Raphson · Goldschmidt · IEEE 754 FP32 architectures
Synthesisable SystemVerilog implementations of the CORDIC algorithm — rotation and vectoring modes, configurable iteration count and fixed-point format
SystemVerilog implementations of 9 numerical formats (FP32 down to FP4) used in neural-network training and inference hardware — includes BF16, FP16, FP8 (E4M3/E5M2), INT8/INT4 and FP4 variants
Synthesisable SystemVerilog implementation of a pre-norm transformer decoder block with KV-cache, plus full verification suite (83 tests passing)