Free SystemVerilog Simulators — What Actually Runs

What this deck covers

1. Why it matters: parsing is not simulating
2. The five tools
3. The support matrix
4. Interactive: which simulator runs my testbench?
5. Verilator 5.020 — what broke, and the workarounds
6. Icarus Verilog 12 — what broke, and the workarounds
7. AMD Vivado simulator (xsim) — the free full-featured option
8. Questa–Altera FPGA Starter Edition — the licence catch
9. slang — a compiler, not a simulator
10. Code that every tool should reject
11. Testbench timing bugs no compiler will find
12. Where the nineteen challenges stand
13. Choosing a simulator — and the disk it needs
14. Set-up recipes

Parsing is not simulating

The starting point was a review of the SystemVerilog coding challenges in three interview-preparation repositories — Interview_FPGA, Interview_DSP and Interview_RTL_LLM_Accelerators. Nineteen .sv files, each a design plus a self-checking testbench.

A full SystemVerilog front end (slang) found the six files that did not compile. It could not find what came next. Once each testbench actually ran — nine in Verilator, the other ten in Vivado xsim 2025.2 — most of them failed:

The five tools

Commercial simulators (Synopsys VCS, Cadence Xcelium, Siemens Questa) support essentially the whole language, and are the reference the other tools are measured against.

The support matrix

✓ works◐ partly✗ fails? not established

^O observed in this exercise^D vendor documentation^K widely known, not re-tested here

The Icarus, Verilator and xsim columns are what those versions actually did with the challenge files (xsim 2025.2 ran the ten that the other two could not); cells marked D come from AMD's UG900 (Appendix B) or, for Questa Starter, Altera's product page and support forum.

Which simulator runs my testbench?

Tick the features your testbench uses. Each simulator's verdict is the weakest cell across your selection.

Presets: plain RTL + self-checking TB · RTL + SVA assertions · class-based TB with coverage · clear

Verilator 5.020 — what broke

Built with verilator --binary --timing --assert. Every row is a real message from a real file.

What did work: concurrent assertions with |=> and $past, --timing delays and events, fork/join, automatic variables in always_ff, DPI-C with a linked C file, and real maths including $exp.

Icarus Verilog 12 — what broke

Compiled with iverilog -g2012. Icarus is the simulator the standalone RTL projects in this GitHub (AI_MMUL_Unit, AXI4_Crossbar, Cache_Controller_MESI, the RISC-V SoC) were verified with — usually under cocotb.

Workarounds already in the RTL projects

• Cache_Controller_MESI: always @(*) in place of always_comb “to prevent iverilog infinite re-evaluation loops when blocks read submodule outputs”, and two mesi_handler instances to “avoid combinational loops through a shared mux in iverilog”.
• AXI4_Crossbar: always @(*) for the same reason.

AMD Vivado simulator (xsim)

Ships in every Vivado edition, including the free Vivado ML Standard. It needs no FPGA project: xvlog, xelab and xsim run from the command line.

Observed with 2025.2 — all ten remaining challenges now run and pass

Everything else the ten needed ran as documented: classes, mailboxes, parameterised virtual interfaces with clocking blocks, named disable across fork branches, ## sequences, break, array arguments, DPI-C, and covergroups with transition, iff and with bins. xsim is also stricter than slang: it rejected a variable driven by an always_ff and another process (three of the original files), an out-of-range constant index, and a module-scope variable used before its declaration — slang passed all three.

Questa–Altera FPGA Starter Edition

Free with Quartus Prime Lite. The licence comes from Altera's Self-Service Licensing Center, is node-locked, and must be renewed every year. The Starter edition is capacity-limited; the paid Altera FPGA Edition raises the limit.

It remains a good simulator for plain RTL with self-checking testbenches, and for mixed VHDL/Verilog designs — but for those, Icarus and Verilator already do the job without a licence to renew.

slang — a compiler, not a simulator

slang parses and elaborates the full IEEE 1800-2017 language and reports errors precisely. Through pip install pyslang it is the quickest way to answer “is this legal SystemVerilog?”.

Use it as a pre-commit lint across every file. Then simulate.

Code that every tool should reject

These were in the challenge files. They are not simulator limitations — the language forbids them, or leaves the result undefined.

Testbench timing bugs no compiler will find

Many of the nineteen challenges needed testbench fixes as well as — or instead of — design fixes. Four patterns kept recurring.

Where the nineteen challenges stand

All nineteen now simulate and pass: nine in Verilator 5.020, the other ten in Vivado xsim 2025.2, which is the only free simulator here that runs them.

Choosing a simulator — and the disk it needs

Disk and drive

• Vivado is the only heavyweight here. A full install runs past 100 GB; choosing just the simulator plus one small device family brings it down to tens of GB. Icarus, Verilator and slang together fit in a few hundred MB.
• Hard disk vs SSD. Vivado launches and installs much faster from an SSD, because it loads thousands of files. Command-line xsim runs on testbenches this size are dominated by compiling and simulating, which a spinning disk handles acceptably. An SSD is a comfort, not a requirement.

Set-up recipes

pip install pyslang
python -c "from pyslang.syntax import SyntaxTree; from pyslang.ast import Compilation
c = Compilation(); c.addSyntaxTree(SyntaxTree.fromFile('tb.sv'))
print([str(d.code) for d in c.getAllDiagnostics() if d.isError()])"

apt-get download verilator && dpkg -x verilator_*.deb vl
export VERILATOR_ROOT=$PWD/vl/usr/share/verilator
ln -s $PWD/vl/usr/bin/verilator_bin $VERILATOR_ROOT/verilator_bin   # wrapper looks here
vl/usr/bin/verilator --binary --timing --assert -j 1 --top-module tb tb.sv [model.c]
./obj_dir/Vtb

sudo apt install iverilog
iverilog -g2012 -s tb -o tb.vvp tb.sv && vvp tb.vvp

source /opt/Xilinx/2025.2/Vivado/settings64.sh   # xvlog, xelab, xsim, xsc
xsc softmax_golden.c                     # builds xsim.dir/work/xsc/dpi.so
xvlog -sv challenge_02_softmax_testbench.sv
xelab softmax_testbench -sv_lib dpi -s snap
xsim snap -R