One real channel, characterised and then equalised all the way to a link budget — and an honest answer about which fix is worth the money when it still does not close.
A transmitter launches a clean rectangular symbol. A receiver, twenty-nine inches later, sees something that barely resembles it. Four mechanisms are responsible, and each is fixed by a different block — which is why it pays to keep them apart.
Copper loss rises as $\sqrt{f}$ as current crowds into a thinner skin; dielectric loss rises roughly as $f$. A square pulse is a wide band, so the channel does not merely shrink it — it smears it across many symbols. That is intersymbol interference, and it dominates everything here.
Every discontinuity sends part of the wave back, and part of that returns again. Energy arriving late is ISI with a longer memory and a less predictable shape.
Unlike the first two, it is not correlated with your own data, so it behaves as noise rather than as ISI — and no equaliser can subtract it.
Moves the sampling instant rather than the level, converting to amplitude error in proportion to the slope of the waveform where you sample it.
Because the chassis, the connector and the laminate are chosen long before the SerDes is, and none of them get cheaper with each doubling of data rate. Equalisation is the part of the problem that lives on silicon, which is the only part that does. That is why every rate increase for twenty years has been paid for with more equalisation rather than with better copper — and also why slide 10, where the board turns out to be the cheaper fix, is worth reading carefully.
The names in the next few slides come from three different bodies producing three different kinds of document, and the distinction is worth having before the history starts. It is commonly assumed they are all flavours of Ethernet. Some are; several of the most frequently cited are not. The sensible place to begin is the one every engineer has physically handled.
Published by PCI-SIG, an industry consortium, and a complete interconnect specification — electrical layer, link layer, transaction layer, configuration model and mechanical form factors — rather than only a physical layer. Its naming is the simplest of the three: a link is a generation and a width, so "Gen4 ×16" is sixteen lanes at the Gen4 rate of 16 GT/s.
The rate is quoted in gigatransfers per second — the raw signalling rate before coding overhead is removed, so always a little above the payload throughput. Each lane is full duplex and carries a differential pair in each direction, which means a ×16 slot is thirty-two pairs, sixty-four conductors, all of which must escape the processor package and cross the board together.
| Generation | Rate per lane | Coding | Payload, ×16 link | Nyquist |
|---|---|---|---|---|
| 1.0 (2003) | 2.5 GT/s | 8b/10b | 4 GB/s each way | 1.25 GHz |
| 2.0 (2007) | 5 GT/s | 8b/10b | 8 GB/s | 2.5 GHz |
| 3.0 (2010) | 8 GT/s | 128b/130b | ≈15.8 GB/s | 4 GHz |
| 4.0 (2017) | 16 GT/s | 128b/130b | ≈31.5 GB/s | 8 GHz |
| 5.0 (2019) | 32 GT/s | 128b/130b | ≈63 GB/s | 16 GHz |
| 6.0 (2022) | 64 GT/s, PAM4 | FLIT + FEC | ≈121 GB/s | 16 GHz |
| 7.0 (draft) | 128 GT/s, PAM4 | FLIT + FEC | ≈242 GB/s | 32 GHz |
Generation 6 doubles the throughput of generation 5 while leaving Nyquist exactly where it was, at 16 GHz, because it moves from two-level to four-level signalling and so halves the symbol rate for a given bit rate. That is precisely the trade slide 11 works through for Ethernet — same channel, twice the data, and a 9.5 dB signal-to-noise penalty to pay for it. PCIe reached the same conclusion as Ethernet, four years later and for the same reason: there was no more bandwidth to be had from the copper.
A graphics or accelerator card in a ×16 slot; an NVMe SSD, which is simply a PCIe device in an M.2, U.2 or EDSFF package rather than a storage interface in its own right; a network adapter at ×8 or ×16; the processor-to-chipset link; and since 2019 CXL memory and accelerators, which run their own protocol over the PCIe electrical layer and inherit its channel problems wholesale. Thunderbolt and USB4 tunnel PCIe too — which is how an external enclosure can hold a graphics card.
Short — a few inches of motherboard to a slot, or a riser card and then a slot — but unusually rich in connectors and unusually strict about interoperability. A Gen5 slot must work with a Gen1 card from any vendor, which is why equalisation is negotiated from a published preset table rather than adapted freely, and why much of the PCIe budget goes on reflections and crosstalk rather than the loss that dominates a backplane.
When the budget runs out, the standard's answer is a retimer: a device that fully recovers clock and data and retransmits them, resetting the loss budget at the cost of latency and power. Distinguish it from a redriver, an analogue amplifier and equaliser with no clock recovery. A redriver improves a channel; a retimer replaces it with two shorter ones.
With that in hand, the two families of names this deck leans on more heavily.
It specifies complete physical layers: coding, electrical interface, medium and compliance tests as one package. The names are systematic once you know the grammar. In 10GBASE-KR: 10G is the rate, BASE means baseband rather than modulation onto a carrier, K says the medium is a backplane, R says the coding is 64b/66b. A trailing digit counts lanes.
| Position | Letter | Means |
|---|---|---|
| Medium | T / K / C | Twisted pair / backplane / twinax copper cable |
| Medium | S / L / E / F | Short-wavelength multimode fibre / long-wavelength single mode / extra-long / fibre generally |
| Coding | X / R | 8b/10b (25% overhead) / 64b/66b (about 3%) |
| Lanes | trailing digit | Absent means one. 100GBASE-KR4 = 100 Gb/s over a backplane, 64b/66b, on four lanes of 25 |
Revisions arrive as lettered amendments — which is where 802.3ap (2007, backplane), 802.3bj (2014, 100G and RS-FEC), 802.3ck (2022, 100G per lane) and 802.3dj (in progress, 200G per lane) come from.
The term most often misread. It is not a physical layer over a medium — it is a chip-to-chip interface, defined so a 10 Gigabit Ethernet MAC's internal bus can cross a few inches of PCB to a separate PHY chip. The name is "ten gigabit attachment unit interface": X is the Roman numeral, AUI a term inherited from 1980s Ethernet. It carries 10 Gb/s of payload as four lanes of 3.125 gigabaud, the extra rate being 8b/10b overhead. XLAUI, CAUI and the later AUI variants do the same job at 40, 100 and 400 Gb/s. "Ran XAUI" means chips talking on a board, not a cable between machines.
The Optical Internetworking Forum publishes Implementation Agreements rather than standards, and its Common Electrical I/O series specifies the electrical interface alone — signalling, channel, transmitter and receiver compliance — with no reference to the protocol running over it. That is the point of them. CEI-28G is the electrical layer a 28 Gb/s lane sits on whether it carries Ethernet, Fibre Channel, InfiniBand or optical transport; it is reused by all of them rather than belonging to any.
| Class | Stands for | Roughly | Typical use |
|---|---|---|---|
| XSR | Extremely short reach | a few cm | Die to die, or chip to an optical engine in the same package |
| VSR | Very short reach | ~10 cm | Chip to a front-panel pluggable module |
| MR | Medium reach | ~50 cm | Chip to chip across a board or a mezzanine |
| LR | Long reach | ~100 cm | Backplane — two connectors, and the worked example of this deck |
IEEE defines the network and its ports; OIF defines the electrical interfaces that connect chips to one another and to optical modules. They are developed in step — CEI-112G and IEEE 802.3ck arrived together and are aligned on rate and channel — so a lane can legitimately be described either way, depending which layer you mean.
One other recurs below: KP4 FEC is the Reed–Solomon code RS(544,514), named after the 100GBASE-KP4 physical layer it was first specified for and now used far beyond it.
XAUI in 2002 ran 3.125 GBd over a channel with perhaps 6 dB of loss at Nyquist, and a fixed two-tap transmit de-emphasis — a switchable current in the output driver — was enough. Nothing about it adapted; a board designer picked a setting from a table.
The step that made modern links possible was 10GBASE-KR in 2007, which standardised three things at once: a three-tap transmit FFE, a receive DFE, and a training protocol by which the receiver tells the transmitter which way to move its taps. Until then equalisation was open-loop and set by hand. After it, a link negotiated its own settings at start-up and 20 dB channels became routine.
CEI-28G around 2011 added the CTLE as a standard receive block and pushed decision feedback to a dozen taps. That is the generation this deck's worked example belongs to, and the last in which a designer can follow every block by hand. What came next changed the character of the problem: 400GbE and CEI-56G moved to PAM4 and made forward error correction mandatory, because the 9.5 dB PAM4 gives away (slide 11) is simply not recoverable by equalisation. 802.3ck and CEI-112G then replaced the analogue slicer with an ADC, moving equalisation into the digital domain where long filters and sequence estimation become affordable.
Every generation bought its rate increase with more equalisation on silicon, not with better copper. The structure of the problem has not changed since 2007: a channel you cannot alter, a pulse response that describes it completely, filters whose taps solve a quadratic minimisation, and a budget that decides whether it works.
Standards do not appear because someone wants a faster number. Each generation was forced by a class of machine that had run out of road — and the shape of the channel changed as much as the rate did.
Until the early 2000s almost everything inside a computer was a wide, slowly clocked, multi-drop parallel bus: PCI at 33 then 66 MHz, PCI-X at 133, parallel ATA, parallel SCSI, a front-side bus. The attraction was a common clock — every receiver samples on the same edge. The problem is that the timing budget does not scale. Sixty-four lines must arrive within a fraction of a clock period, so the skew between them (length mismatch, crosstalk, clock jitter) must shrink with the clock while its physical causes do not. And a multi-drop bus has a stub at every load, and every stub is a reflection. Ultra-320 SCSI needed heroic measures; Ultra-640 was specified and essentially never shipped.
The escape was to serialise: one differential pair instead of sixty-four single-ended lines, clock embedded rather than distributed, point-to-point rather than multi-drop. That trades pin count for rate and removes skew-between-bits and load stubs in one move — at the cost of a clock recovery loop in every receiver, and of putting the whole timing budget on one channel whose loss you now have to fight.
| Era | Machines | The channel | What limited it |
|---|---|---|---|
| to ~2003 | PCI and PCI-X slots, parallel ATA and SCSI, front-side buses | Wide multi-drop parallel bus, common clock | Skew between bits and stub reflections — neither scales with the clock |
| 2000–2005 | PCIe 1.0, SATA, SAS, InfiniBand, XAUI in early routers | Short point-to-point differential pairs, ~6 dB | Connectors, pair routing discipline, a CDR per lane |
| 2005–2012 | ATCA shelves, core routers, blade servers | 20–40 inches of backplane through two connectors | The same card must work in every slot → equalisation had to adapt. Then connector crosstalk |
| 2012–2020 | Fixed-config switches in Clos fabrics; NVMe and CXL servers | 6–12 inches, package to front-panel cage | Rate rising faster than reach falling; package and board escape for hundreds of lanes |
| 2020– | Accelerator clusters, 400G/800G optics | A handful of inches, or no PCB at all | Reach, power per bit, and the cost of converting to light |
ATCA telecom shelves, core routers such as the Cisco CRS-1 and Juniper's T-series, blade servers from IBM and HP: all share a passive backplane with line cards plugged into it, and that architecture creates a problem fixed settings cannot solve. The same line card must work in every slot. Slot 1 might be six inches from the switch card and slot 16 thirty-six inches, through two connectors either way, and no factory setting is right for both. The receiver has to discover the channel it has been given — which is exactly what 10GBASE-KR's training protocol provides.
A second constraint made equalisation more valuable still. A chassis is a ten-year investment and its backplane is passive and unserviceable, while the line cards are replaced every few years — so a backplane etched in 2005 had to carry the SerDes of 2012. That is precisely why the money went into equalisation rather than into new copper. The limiting impairment turned out to be crosstalk, because a backplane connector carries dozens of pairs through one shroud; that drove a generation of connector redesign, and eventually architectures that deleted the midplane by plugging line cards directly into fabric cards at right angles.
Hyperscale operators replaced the big chassis router with many small fixed-configuration switches in a Clos fabric. Thirty inches of backplane became six to twelve inches from package to front-panel cage — which should have made life easier and did not, because the rate went 10 → 25 → 50 Gb/s per lane over the same period. The bottleneck moved: switch radix grew roughly sixteen-fold in a decade, so getting hundreds of lanes out of the package and across the board became as hard as getting them down the channel. Meanwhile PCIe became a storage interface through NVMe and a memory interface through CXL, pushing its channel budgets into genuine difficulty and making retimers ordinary.
At 112 Gb/s per lane the reach an equaliser can rescue has fallen to a handful of inches of ordinary laminate, and four responses are visible at once: cabled backplanes routing twinax from the package over the board to the front panel; co-packaged optics; linear-drive optics deleting the module's retimer; and chiplet interfaces keeping the fastest links inside the package. The largest accelerator racks now carry thousands of copper cables in a scale-up domain precisely because optics at that density would cost more power.
Every era solved its channel problem by moving the difficulty somewhere cheaper. The parallel bus moved it from pin count to rate. The backplane era moved it from copper to silicon, because silicon got cheaper every year and a ten-year chassis did not. The data-centre era moved it from the chassis to the fabric topology, replacing one enormous channel with many short ones. The current era is moving it off the board entirely, into cable and into light. Equalisation is what made each of those moves survivable while the next one was being worked out.
Ethernet and the OIF agreements are one branch of the family. PCI Express is the other one most engineers meet, and it faces the same physics under quite different commercial constraints. A backplane Ethernet link joins two devices chosen by the same architect; a PCIe link crosses a socket, a connector and an add-in card from a different vendor, and must interoperate with parts designed a decade apart. It cannot simply let both ends adapt freely and hope.
Its answer, from PCIe 3.0 in 2010, is a negotiated preset table: rather than requesting arbitrary tap movements, the receiver asks the far-end transmitter for one of eleven predefined combinations of de-emphasis and pre-shoot, agreed over a four-phase link equalisation procedure. More constrained than 10GBASE-KR's continuous negotiation, and deliberately so — a finite, published set of transmitter behaviours is what makes cross-vendor interoperability testable.
| Generation | Rate / lane | Year | What was added |
|---|---|---|---|
| PCIe 1.0 / 2.0 | 2.5, 5.0 GT/s | 2003, 2007 | 8b/10b coding; fixed de-emphasis chosen by the platform |
| PCIe 3.0 | 8 GT/s | 2010 | 128b/130b, transmitter presets and the four-phase link equalisation procedure — PCIe becomes an equalised link |
| PCIe 4.0 / 5.0 | 16, 32 GT/s | 2017, 2019 | Tighter channel budgets; retimers become common; connector and card loss start to dominate |
| PCIe 6.0 | 64 GT/s | 2022 | PAM4, FLIT framing, and a deliberately lightweight FEC backed by link-level retry |
| PCIe 7.0 | 128 GT/s | 2025 (draft) | PAM4 at 64 GBd; reach becomes acute and optical options enter the discussion |
Both moved to PAM4; both had to add FEC to survive it; they made opposite trades. Ethernet tolerates the ~100 ns a Reed–Solomon KP4 decoder costs, because that is nothing beside the latency of the network it sits in. PCIe is a load-store fabric where a processor may be stalled waiting for the answer, so latency is part of the contract. PCIe 6.0 therefore pairs a much lighter FEC with a CRC and link-level retry for what it misses. Same physics, same constellation, different answer, because the cost function is different.
The pattern repeats elsewhere, and the interesting axis is reach rather than rate. USB grew from 5 Gb/s in 2008 to 20 Gb/s per lane with USB4, then to 80 Gb/s in USB4 v2 by adopting three-level PAM3 — buying throughput with less SNR penalty than PAM4 while still needing real equalisation over a consumer cable. SAS reached 22.5 Gb/s; InfiniBand went 25 Gb/s NRZ at EDR to 50 and 100 Gb/s PAM4 at HDR and NDR; DisplayPort and HDMI carry comparable rates over cables with no ground reference to speak of.
At the far end sits UCIe, the die-to-die interface standardised from 2022: a couple of millimetres of silicon interposer instead of tens of inches of laminate. At that reach the loss is negligible, the equalisation is nearly nothing, and the problem becomes parallelism and power per bit. That is the direction all of these are being pushed — as the rate climbs, the reach equalisation can rescue falls, and the answer is either to shorten the copper or to stop using it.
A conventional two-card backplane topology: transmit package, six inches of line card, a connector, eighteen inches of backplane, a second connector, four inches on the receiving card, receive package. 28.8 inches of 100 Ω differential stripline on Dk 3.7 laminate at 163 ps per inch — a flight time of 4.7 ns, or 131 unit intervals. There are always more than a hundred symbols in flight at once, which is worth remembering when reasoning about what a reflection does.
Three things to read off the S-parameters before designing anything. Insertion loss at Nyquist is the headline difficulty. Return-loss ripple is the signature of energy bouncing between the two connectors; because the round trip is many unit intervals, those echoes land as isolated ISI terms far from the cursor, exactly where a five-tap DFE cannot reach them. And mode conversion, the $\mathbf{S}_{cd}$ block of the companion deck, matters here for a reason specific to equalisation: converted energy is energy the receiver never sees, so it shrinks the cursor without ever appearing in $S_{dd21}$.
Which is why characterisation is done on a multiport fixture. Near-end and far-end crosstalk from the neighbouring lanes are aggregated into one figure of merit, the integrated crosstalk noise, and it enters the budget on slide 09 as 3.0 mV rms. On this channel it turns out to be the largest single term.
A dielectric constant of 3.7 and a loss tangent of 0.0079 are not arbitrary numbers — they identify a class of material. Dielectric loss is, to a good approximation,
$$\alpha_d \approx 2.3\, f\,\sqrt{\text{Dk}}\ \text{Df} \quad \text{dB per inch}, \qquad f \ \text{in GHz},$$
so Df sets the slope of the channel directly while Dk sets the propagation delay and, through it, how much copper a given reach costs you.
| Laminate | Dk | Df | Dielectric loss at 14 GHz | Typically used for |
|---|---|---|---|---|
| Standard FR-4 | ≈4.3 | ≈0.022 | 1.47 dB/in | Up to a few Gb/s — PCIe 1.0/2.0, USB 3.0, XAUI |
| Isola FR408HR | 3.65 | 0.0092 | 0.57 dB/in | 8–10 Gb/s — PCIe 3.0, 10GBASE-KR |
| This deck's channel | 3.70 | 0.0079 | 0.49 dB/in | Mid-loss; fine at 10 Gb/s, marginal at 28 |
| Isola I-Speed | 3.53 | 0.0060 | 0.36 dB/in | 16–28 Gb/s — PCIe 4.0/5.0, CEI-28G |
| Panasonic Megtron 6 | 3.55 | 0.0045 | 0.27 dB/in | 25–28 Gb/s backplanes; the low-loss remedy of slide 10 |
| Rogers RO4350B | 3.48 | 0.0037 | 0.22 dB/in | RF and mixed-signal boards where Dk stability matters most |
| Isola Tachyon 100G | 3.02 | 0.0021 | 0.12 dB/in | 56 Gb/s PAM4 and above — CEI-56G, PCIe 6.0 |
| Panasonic Megtron 7 | 3.35 | 0.0020 | 0.12 dB/in | 112 Gb/s per lane — 802.3ck, CEI-112G |
Foil is deliberately roughened so it sticks to the resin, and at microwave frequencies the current follows that surface rather than cutting across it. Standard foil (5–7 µm profile) can add half again to the smooth-conductor loss at 14 GHz; reverse-treated brings it down, VLP further, hyper-VLP further still. A board on excellent resin with ordinary foil can lose to one on worse resin with better copper.
Resin reinforced with woven glass — and glass and resin differ in Dk, roughly 6 against 3. A pair with one conductor over the bundles and the other over resin sees two propagation velocities: intra-pair skew, hence mode conversion (companion deck, slide 17). It accumulates with length, which is why long pairs are routed at a small angle to the weave or on spread-glass styles such as 1078 and 3313.
The one surprising row above is Rogers RO4350B: at 0.22 dB/in it is lower loss than the Megtron 6 that slide 10 recommends — and yet nobody builds a backplane out of it. The reasons are all system fit rather than decibels.
It is engineered for Dk stability (±0.05 over temperature and lot), which matters when the dielectric constant sets a filter passband or an antenna length and is of no use whatever to a serial link. Its Dk of 3.48 is also too high: digital laminates chase low Dk deliberately, because a lower dielectric constant allows wider traces at the same 100 Ω differential impedance, and conductor loss falls as trace width rises.
And the conductor term is no detail here — it is comparable to the dielectric term and is dominated by foil roughness, where differences of 0.1–0.2 dB/in between grades are typical. So the 0.05 dB/in RO4350B gains on Megtron 6 in the dielectric is smaller than the foil advantage it does not come packaged with: the digital vendors sell core, prepreg, glass style and foil profile as one qualified system, and the RF vendors offer a narrower range.
RF laminates are not offered in the spread-glass constructions that control intra-pair skew — a single-ended RF line does not care about weave, a differential pair very much does. And the bondply system and reliability qualification target thin, low-layer-count boards, not a forty-layer backplane built by sequential lamination with tens of thousands of plated through-holes to survive thermal cycling. The ceramic filler is abrasive enough to matter to drill life, and the laminate costs several times as much per square foot.
As an RF island hybrid-laminated into an otherwise digital stackup — the sensible way to use them when a board needs both. The PTFE-based laminates (RO3003, RT/duroid) take every one of these trade-offs further in the wrong direction: lower loss again, but poorer dimensional stability, special processing for adhesion, and worse through-hole reliability in a thick board.
Up to a few Gb/s, ordinary FR-4 and ordinary foil. At 8–10 Gb/s, improved FR-4 with reverse-treated foil. At 16–28 Gb/s, a genuine low-loss laminate, VLP copper and spread glass. At 56 and 112 Gb/s per lane, ultra-low-loss resin with hyper-VLP foil — and a much shorter channel, because at those rates no material saves a backplane. Materials bought perhaps 15 dB across twenty years, while the loss at Nyquist of a fixed length of copper roughly tripled over the same period.
The verdict on RF laminates is easier to see once the rest of the board is on the table, because almost nothing about a high-speed digital stackup is chosen for signal integrity alone. It is a compromise between routing density, power delivery, mechanical rigidity and manufacturing yield — and the SI engineer arrives late and negotiates.
A modern switch or accelerator package has thousands of balls on a 1 mm or finer pitch, several hundred pairs of them high-speed. Every pair must thread between the antipads of the balls around it, and only one or two traces fit in that channel. The only way to escape hundreds of pairs is a few per layer across 20 to 40 layers — decided by the ball map, not the dielectric.
Conductor loss falls as the trace widens, so an SI engineer left alone would use very wide traces. The escape channel forbids it: 4 to 6 mil is whatever fits between antipads, where the loss calculation would prefer 8 to 12. This is the sharpest difference from RF, where a line can be as wide as the substrate allows because there are dozens of nets, not thousands.
It follows from layer count, then is pinned from three directions: press-fit connectors are qualified for a thickness range and the compliant pin will not seat outside it; a large card must be stiff enough not to sag or flex on insertion; and the plating aspect ratio (thickness ÷ drill) has a limit, beyond which you need a bigger drill — which enlarges the antipad, which takes away the routing channel you were trying to create.
A thick board means long via barrels, and a signal entering at layer 3 and leaving at layer 6 leaves most of the barrel dangling as a stub. In RF you would simply use a thin substrate and the problem would not arise. Here the thickness is not available as a design variable, so the industry invented a second drilling operation to remove the unused copper afterwards — at extra cost, with its own tolerance, leaving 6 to 10 mil of residual stub. Slide 04 shows what happens when it is skipped.
| High-speed digital board | RF board | |
|---|---|---|
| Layer count | 20–40, occasionally more; set by package escape | 2–8; often a single ground plane |
| Thickness | 2.5–6 mm, fixed by layer count, connectors, stiffness, plating aspect ratio | 0.25–1.5 mm, chosen freely to set line width and radiation |
| Trace width | 4–6 mil, set by the escape channel between antipads | Tens of mils, set by impedance and loss |
| Nets | Thousands, all at one controlled impedance | Tens, individually tuned |
| Bandwidth | DC to beyond Nyquist, broadband | A band, often a narrow one |
| Vias | Tens of thousands; each an impairment to be back-drilled | Few; often a deliberate design element |
| What must be stable | Loss slope and impedance across a huge board and a long production run | Dk, tightly, over temperature and lot |
| Shares the stackup with | Dozens of power rails, plane splits, decoupling | Little else |
Read down that table and the verdict on RO4350B becomes almost inevitable. A material whose distinguishing virtue is tightly controlled Dk, supplied in thin constructions for boards with a handful of layers, is answering a question the digital designer never asks, in a form he cannot use, at a price that scales with an area he cannot avoid.
A plated through-hole that carries the signal only part of the way down leaves the rest of the barrel hanging off the path as an open-circuited stub. An open stub is a quarter-wave short: at the frequency where its length is a quarter wavelength it presents a near short-circuit across the line, and the channel develops a deep notch.
$$f_{\text{notch}} = \frac{1}{4\,\tau_{pd}\,\ell}, \qquad \tau_{pd} = 163\ \text{ps/inch}.$$
Drag the length. Watch where the notch lands relative to Nyquist.
On the modelled channel the as-fabricated 110 mil stub adds about 25 dB at Nyquist, taking $|S_{dd21}|$ from −33.3 dB to −58.2 dB. No amount of equalisation recovers a notch: the information at those frequencies is gone, not merely attenuated. Back-drilling is not an optimisation here, it is the difference between a link and a brick.
Insertion loss tells you how much of a sine wave survives. It does not directly tell you what a receiver sees, because a receiver does not sample sine waves — it samples one symbol at a time, in the presence of all the others. The object that answers that question is the pulse response: the waveform produced by sending a single one-UI symbol and nothing else. Inverse-transform $S_{dd21}$, convolve with a one-UI rectangle, and there it is.
Sample that waveform once per unit interval at the phase that maximises the peak, and the resulting sequence is the whole story:
The largest sample — the part of the symbol that arrives when it is supposed to. Here 0.199 of the transmitted amplitude.
Energy that arrived early, landing on symbols not yet decided. The DFE can never touch these. First one: 0.117.
Energy still arriving one, two, ten symbols later. First one: 0.145, and the tail runs for dozens of UI.
The cursor is 0.199 and the sum of the absolute values of every other tap is 0.636 — more than three times larger. The worst-case eye opening is twice the difference, which comes out at −0.87. A negative eye opening is not a small eye: it means that for some patterns of neighbouring data the receiver sees the wrong sign entirely. Nothing about this link works without equalisation.
Four blocks, each good at something the others are not, and each with a price.
| Block | Removes | Cannot remove | Costs |
|---|---|---|---|
| CTLE analogue, in the front end | Broadband slope, very cheaply | Anything with structure — reflections, isolated echoes | Cursor amplitude. It attenuates low frequencies rather than amplifying high ones |
| Transmit FFE FIR before the channel | Pre-cursor and near post-cursor ISI, before crosstalk is added | Anything it cannot see; it has no knowledge of the receiver's noise | Transmit swing, through the peak-power constraint $\sum|c_i| \le 1$ |
| Receive FFE FIR after the channel | Pre-cursor ISI and long tails, with many taps available — and it collects signal energy the channel scattered | Nothing in principle, but it cannot beat the matched-filter bound | Noise enhancement — the gap between coherent signal gain and incoherent noise gain: 0.75 dB here |
| DFE feedback on decisions | Post-cursor ISI exactly, with no noise penalty at all — the decision is noiseless by construction | Pre-cursor ISI, ever. It acts only on symbols already decided | Error propagation, and a hard timing path on the first tap |
It is tempting — and wrong — to call a receive FFE a device that removes interference at the cost of amplifying noise. When it forms a weighted sum of several successive samples, the signal contributions add coherently: the pre- and post-cursor samples are not noise, they are the same symbol arriving at the wrong time, so lining them up adds their amplitudes directly. The noise, uncorrelated sample to sample, adds only in root-sum-square. Combine $k$ comparable samples and signal grows as $k$ while noise grows as $\sqrt{k}$.
That is the matched-filter mechanism, and it has the matched-filter limit: $\mathrm{SNR} \le 2E/N_0$, set by the total energy in the pulse. A linear equaliser cannot beat that bound and usually falls short, because it must also drive the interference to zero and on a channel with deep nulls those two objectives conflict. The shortfall is what "noise enhancement" means. The 9-tap MMSE design here has a tap norm of about 34 — alarming if it were a penalty — but the same taps raise the cursor by a comparable factor. The net cost is the ratio: 0.75 dB. Quoting the tap norm alone would overstate it by more than twenty decibels.
A DFE subtracts the known contribution of symbols it has already decided, so it cannot touch pre-cursor ISI — that comes from symbols it has not decided yet. A receive FFE can, at the cost of noise enhancement. A transmit FFE can, at the cost of swing. Splitting the work so the transmitter handles pre-cursors and the feedback path handles post-cursors is not arbitrary: it puts each impairment where the cheapest remedy is.
This is why the classical optimum has the structure it does. Forney's decomposition of the maximum-likelihood receiver puts a whitened matched filter at the front — the energy collection above — and follows it with a detector for the remaining causal interference. The MMSE decision-feedback equaliser is its practical descendant, and it beats the best purely linear equaliser on every lossy channel. What stops it reaching the matched-filter bound in practice is error propagation, not the mathematics.
The real pulse response of the modelled channel, equalised in the browser. Choose a CTLE setting, switch the transmit FFE in or out, set the number of feedback taps, and adjust the noise the receiver has to live with. Everything below is computed from the sampled pulse response, not looked up.
Three things are worth trying. Turn the CTLE down and watch the cursor rise while the ISI rises faster. Turn the transmit FFE off and watch the pre-cursors reappear where no DFE can reach them. And push the DFE past about eight taps and watch the returns flatten out — the tail is long, but by then it is small compared with the crosstalk.
Tracking the pulse response through the chain, set out twice on purpose. The left group is in millivolts at the receiver input, which is where a budget has to be written; the right group normalises each stage to its own cursor, which is where the shape is visible without the scaling getting in the way.
| Stage | Cursor | ISI (rms) | Non-ISI noise | ISI ÷ cursor | Eye ÷ cursor |
|---|---|---|---|---|---|
| Channel only | 79.49 mV | 88.18 mV | 3.50 mV | 3.199 | -4.397 |
| + CTLE | 27.85 mV | 21.33 mV | 1.84 mV | 1.995 | -1.989 |
| + transmit FFE | 12.94 mV | 7.34 mV | 1.84 mV | 1.114 | -0.228 |
| + DFE, five taps | 12.94 mV | 1.12 mV | 1.84 mV | 0.349 | 1.303 |
| Block | Scales the cursor? | Why |
|---|---|---|
| CTLE | Yes, and it must | A passive-shaped analogue filter with fixed headroom. Its high-frequency gain is about unity, so the only way to present a rising response is to attenuate everything below. But it attenuates the incoming noise and crosstalk by nearly the same factor (−5.6 dB over the noise bandwidth), so most of that cursor reduction is not an SNR loss |
| Transmit FFE | Yes, and it must | Hard peak-power limit: $\sum|c_i| \le 1$, so every unit of correction is subtracted from the main tap. The noise it fights is added downstream and does not scale with it — so this attenuation is a real SNR loss, the most expensive decibels in the chain |
| Receive FFE | No, not meaningfully | Its gain is arbitrary: a VGA and the slicer threshold follow it and scale together. Only the ratio of signal gain to noise gain matters (slide 06), which is why normalising its output to unity is fair |
| DFE | No | It subtracts rather than scales. Cursor untouched, noise untouched — the thing subtracted is a decision, not a waveform |
It is often said that equalisation makes the interference shrink faster than the signal does. That is a statement about the cursor, and the cursor is not well defined — it depends where you put the gain, and sliding the AGC makes it whatever you like. The invariant statement is about ratios: every linear block trades signal-to-noise ratio for signal-to-ISI ratio. Measured against the noise that is not correlated with the data — thermal, crosstalk, quantisation, jitter converted through the slope — the signal falls monotonically, from 27.1 dB at the channel output to 16.9 dB after the transmit FFE, and no linear operation can reverse that. What is bought in exchange is the other ratio: signal to residual ISI climbs from -0.9 dB to 21.3 dB. The link works when the two together are good enough — and both matter only over the bandwidth the signal actually occupies.
The DFE is the only block whose signal-to-noise line is flat: it improves the ISI ratio by 16.3 dB at no cost in signal-to-noise whatsoever. Every other block pays. And the transmit FFE, judged alone, looks like a poor bargain — it gives up 6.7 dB of SNR to buy only 2.6 dB of signal-to-ISI. Run the chain without it and five feedback taps take Q only from 1.30 to 1.69, because what remains after the CTLE is dominated by pre-cursors the feedback path cannot reach. The transmit FFE is not there to open the eye by itself; it is there to clear the pre-cursors so that the block which is free can do its work. Together they take Q from 1.30 to 6.01.
$[\,0.040,\ -0.340,\ 0.620\,]$ — two pre-taps zero-forcing the first two pre-cursors, normalised so $\sum|c_i| = 1$. The main tap at 0.62 is the de-emphasis penalty, made visible.
$[\,0.301,\ -0.368,\ -0.195,\ -0.032,\ 0.005\,]$. A second tap of −0.37 is large enough that error propagation is a real risk — one reason FEC and decision feedback are usually specified together.
The feedback path must settle within one unit interval — 35.7 ps — from slicer output back to slicer input. That puts the first tap on the critical path of the whole receiver, which is why it is usually unrolled: both possible answers computed speculatively in parallel, with the decision selecting between them after the fact.
An open eye is necessary but not sufficient. What decides the error rate is the ratio of the eye opening to everything that moves the received level around, and those contributions must be referred to a common point. Referring them to the receiver input, where the cursor is 12.9 mV out of an 800 mV transmitted swing:
| Contribution | Value | Where it comes from |
|---|---|---|
| Crosstalk | 1.58 mV rms | 3.0 mV of integrated crosstalk noise from neighbouring lanes, shaped by the CTLE |
| Residual ISI | 1.12 mV rms | What the equalisers left behind, treated statistically rather than worst-case |
| Receiver noise | 0.95 mV rms | 1.8 mV of front-end noise, shaped by the same filter (−5.6 dB over the noise bandwidth) |
| Jitter | 0.10 mV rms | 350 fs rms of random jitter, converted through the slope at the sampling instant |
| Total | 2.15 mV rms | Root-sum-square |
Signal 12.9 mV over noise 2.15 mV gives $Q = 6.01$, a bit error rate near $10^{-9}$. The conventional target for an uncorrected link is $10^{-12}$, which needs $Q = 7.03$. This link is 1.36 dB short.
The $Q$ used here is the Q-factor of digital and optical communications, and it has nothing to do with the quality factor of a resonator. It is named after the Gaussian tail function $Q(x) = \int_x^\infty \phi(u)\,du$ and defined as
$$Q = \frac{\mu_1 - \mu_0}{\sigma_1 + \sigma_0},$$
which for a symmetric binary signal is simply half the eye opening over the rms noise. Then $\mathrm{BER} = \tfrac12\,\mathrm{erfc}(Q/\sqrt2)$, so $Q = 7.03$ is $10^{-12}$ and $Q = 6$ is about $10^{-9}$. Optical work quotes it in dB as $20\log Q$, which invites a further confusion with electrical SNR in power terms.
The collision genuinely bites anyone working across disciplines — in an atomic clock the fractional frequency stability depends on the resonator $Q$ and on SNR, and both appear in the same expression, so reading "Q" here as the resonator quantity gives a sentence that is wrong in a plausible-looking way. Where the ambiguity matters, quote the error rate directly, or use the IEEE 802.3 channel operating margin, which expresses the same judgement in dB and is defined in the standard rather than by convention. This deck keeps $Q$ because every SerDes datasheet and optical link budget uses it — but it means the communications Q-factor throughout, never the resonator one.
Crosstalk is the largest term, residual ISI is second and receiver noise third. That ordering matters: it says the link is short of margin mostly because of its neighbours and only partly because of what the equalisers left behind. Removing every last scrap of residual ISI would take the total from 2.15 mV to about 1.8 mV — worth roughly four tenths of a decibel, nothing like the shortfall. The next slide checks that arithmetic against every alternative.
Seven candidate remedies, each re-run through the whole chain from the channel model outwards, so the margin figures are computed rather than estimated.
| What you change | Loss at Nyquist | Q | Margin to $10^{-12}$ |
|---|---|---|---|
| As built | −33.3 dB | 6.01 | −1.36 dB |
| Halve the crosstalk (connector + pair pitch) | −33.3 dB | 7.77 | +0.87 dB |
| Low-loss laminate (Df 0.005 → 0.003) | −28.0 dB | 8.98 | +2.12 dB |
| Shorten the backplane 18″ → 13″ | −29.3 dB | 8.52 | +1.67 dB |
| Ten DFE taps instead of five | −33.3 dB | 6.20 | −1.10 dB |
| Add a 9-tap receive FFE (the ADC-DSP answer) | −33.3 dB | 6.34 | −0.90 dB |
| Low-loss laminate + halved crosstalk | −28.0 dB | 11.38 | +4.18 dB |
A lower-loss laminate lifts the cursor by reducing the slope the equalisers have to undo. Five inches off the backplane does much the same, often more cheaply. Halving the crosstalk attacks the largest single term directly. Any one of the three closes the link.
Doubling the DFE taps buys 0.26 dB. Adding a nine-tap receive FFE — the block that defines a modern ADC-DSP receiver, and the obvious thing to reach for — buys 0.46 dB, and still leaves the link short.
The block that fixed the last problem is rarely the block that fixes the next one. A link short of margin is short for a reason; the budget names the reason; and the instinct to reach for more equalisation is the instinct to solve the problem you solved last time. On a channel dominated by ISI rather than crosstalk this table would look entirely different — which is exactly why you build the budget first.
The obvious way to double throughput without doubling the Nyquist frequency is to send two bits per symbol. PAM4 does exactly that: four amplitude levels at the same 28 GBd, across the same 14 GHz of channel. The channel does not get any worse. The signalling does.
Four levels across the same peak-to-peak swing leave three eyes, each one third the height of the single NRZ eye:
$$20\log_{10} 3 = 9.54\ \text{dB}$$
of signal-to-noise ratio given away before anything else is considered — and it is not recoverable by equalisation, because it is a property of the constellation rather than of the channel. On this channel $Q$ falls from 6.01 to 2.00, and the raw error rate rises from $10^{-9}$ to about $3\times10^{-2}$.
An error rate of one in thirty is not a link. The Reed–Solomon KP4 code, RS(544,514) over GF($2^{10}$), takes a pre-correction error rate of about $2.4\times10^{-4}$ down below $10^{-15}$, and PAM4 links are budgeted to that threshold instead of to $10^{-12}$. Even so this channel does not reach it: the required $Q$ is 3.60 and the available $Q$ is 2.00, a shortfall of 5.1 dB.
| Channel change | Loss at Nyquist | Q | Margin to the KP4 threshold |
|---|---|---|---|
| PAM4, as built | −33.3 dB | 2.00 | −5.08 dB |
| PAM4 + low-loss laminate | −28.0 dB | 2.99 | −1.60 dB |
| PAM4 + low-loss + 13″ backplane | −25.1 dB | 3.97 | +0.84 dB |
| PAM4 + all of the above, plus a receive FFE | −25.1 dB | 6.30 | +4.87 dB |
The lesson the industry learned between 2015 and 2020: PAM4 does not let you run twice the data over the channel you already have. It lets you run twice the data over a channel roughly 8 dB better than the one you already have, in exchange for a coding layer, a larger latency budget and a considerably more complicated receiver.
Nothing on slide 06 can be set from a datasheet. Manufacturing spread, temperature, the particular board and the particular connector all move the channel, so every tap in a modern link adapts. The mechanism is the least-mean-squares algorithm of the digital-filter companion deck, usually in its sign-sign form: take the sign of the error between the sampled level and the decided level, take the sign of the data in the relevant tap position, multiply, accumulate. No multiplier, no knowledge of the channel, and it converges to the same minimum of the same quadratic bowl the Wiener–Hopf equations describe.
The receiver has the error signal in hand — the difference between what it sampled and what it decided — so CTLE setting, FFE taps and DFE taps can all track the channel while data flows.
The transmitter has no idea what the receiver saw. So the standards define a link training phase: before data flows, the receiver requests increment, decrement or hold on each transmit tap over a control channel, and the transmitter reports what it did. A few milliseconds, re-run on every link-up.
The clock and data recovery loop chooses the sampling phase, and the equaliser adapts to whatever phase it is given — while the phase detector sees a waveform shaped by whatever the equaliser is currently doing. The two loops can and do fight, and a link that trains to a stable but poor setting (the wrong lock point, an eye centred half a unit interval from the best one) is a common and deeply unpleasant failure mode. Bandwidth separation between the loops is the usual defence.
The 224 Gb/s per lane generation keeps PAM4 and doubles the symbol rate again, to around 112 GBd, putting Nyquist at 56 GHz. Copper at that frequency is unforgiving, and the practical consequence is that the reach of an electrical channel keeps shrinking: a backplane of the kind modelled here is already out of the question, and even the few inches from a switch die to a front-panel cage have become a design problem rather than a piece of routing.
MLSE — instead of equalising then slicing, search for the most likely transmitted sequence given the known channel response. Worth a few dB over a DFE, at considerable digital power.
Concatenated and soft-decision schemes replacing the hard-decision Reed–Solomon codes that have served since 2017 — more coding gain, at the cost of latency and power.
Co-packaged optics move the electrical-to-optical conversion into the switch package; linear-drive pluggables remove the retimer so the host SerDes drives the optical engine directly. Both change the problem from equalising twenty inches to equalising two.
Take that third response to its conclusion and you arrive at the chiplet. If the expensive part of a link is the channel, the cheapest possible channel is a couple of millimetres of wiring on a silicon interposer or an embedded bridge, with bumps on a pitch measured in tens of micrometres. At that reach the loss is negligible across the whole band — and you stop needing the apparatus this deck is about. No CTLE, no feedback taps, no clock recovery loop per lane: a forwarded clock will do, because the lanes are short and matched enough that skew between them is a few picoseconds. Often the signalling is not even differential, because there is no common-mode environment to reject.
What you buy with the power you no longer spend on equalisation is width. A long-reach SerDes at 112 Gb/s costs several picojoules per bit; a die-to-die link over an advanced package costs a fraction of one. Spend the same power at a fortieth of the energy per bit and you can afford hundreds or thousands of lanes instead of dozens — which is why nobody quotes gigabits per lane for a chiplet interface. They quote bandwidth density, terabits per second per millimetre of die edge, because the edge is the scarce resource. The design problem inverts: from "how do I recover a signal that crossed thirty inches" to "how many wires fit along this shoreline, and how little energy can I move a bit with".
| Advanced package | Standard package | Board SerDes | |
|---|---|---|---|
| Medium | Silicon interposer, bridge or fine-pitch fanout | Organic substrate | Laminate, connectors, sometimes a backplane |
| Bump / ball pitch | Tens of µm | ≈100 µm | Hundreds of µm at the package ball |
| Reach | A couple of mm | Up to a few tens of mm | Inches to tens of inches |
| Signalling | Single-ended, forwarded clock, little or no EQ | Single-ended, some EQ | Differential, full equaliser chain, CDR per lane |
| What is scarce | Die edge and bump count | Substrate routing | Channel loss budget |
UCIe standardises this across both package classes so dies from different vendors can in principle be assembled into one part; OCP's Bunch of Wires takes a similar line. The proprietary equivalents came first and ship in volume — the on-package fabric between compute and I/O dies in AMD's processors, the die-to-die links between Intel's tiles, the interconnects joining accelerator dies in the largest training parts. The motivation is not mainly signalling: a reticle has a maximum size, yield falls sharply with die area, and analogue and I/O circuits do not benefit from a leading-edge process the way logic does. The signalling advantage is a consequence of the packaging decision rather than its reason — but a large one.
Chiplets do not abolish the problem, they relocate it. Every bit crossing two millimetres of interposer still has to leave the package eventually, and the link that takes it out is harder than before because the package is denser and hotter and the rate has risen. The effect is to concentrate the difficulty: fewer, faster, more aggressively equalised external links, surrounded by a great many nearly-free internal ones.
The processor-to-memory interface is the one place where the wide, single-ended, common-clock parallel bus of slide 02a never went away. DDR5 runs a 64-bit data path plus check bits at several thousand megatransfers per second, and is subject to everything that killed the parallel bus elsewhere: skew between bits, stubs wherever more than one module hangs off a channel, and a pin count that has become a dominant packaging constraint — a server processor with a dozen channels spends well over a thousand pins on memory alone.
It has survived by importing the serial world's toolkit. Modern DRAM trains per-bit timing and reference levels at initialisation, and DDR5 specifies a decision-feedback equaliser on the DRAM's data receivers — the block from slide 06, in the least likely place. But the rate still rises while the number of modules a channel can carry falls, which is the capacity-versus-bandwidth bind.
A buffer chip on the module accepts a few high-rate serial lanes and drives conventional DRAM behind it — collapsing pin count and removing the multi-drop stub at a stroke. IBM's Open Memory Interface has done this in shipping POWER systems for years, reaching hundreds of GB/s per socket over a handful of lanes. More visibly, CXL-attached memory puts DRAM behind what is electrically a PCIe link, and adds pooling across hosts and mixed media behind one interface.
HBM stacks DRAM dies and connects them over a thousand-odd wires at single-digit gigabits each, across a couple of millimetres of interposer — the chiplet answer applied to memory. It reaches bandwidths no pin-limited external interface can approach, and pays in capacity, cost and the impossibility of upgrading it after manufacture.
This has been tried before. Fully Buffered DIMMs put an advanced memory buffer on every module in the mid-2000s and were abandoned over power and, above all, latency — every hop through a buffer costs time a processor stalled on a load cannot hide. That is why CXL memory is deployed as a capacity tier rather than a replacement for the direct channels: the round trip is roughly double a native DDR access. The likely settlement is that memory stops being one thing — a near tier in the package, wide and parallel and fast; a far tier behind a serial link, large and pooled and slower; conventional modules squeezed between them.
CXL is not a new electrical interface at all: it runs on the PCIe physical layer and reuses its link training, the two ends negotiating into CXL mode during the same sequence that would otherwise bring up an ordinary PCIe link. Everything on slide 01b about presets, retimers and channel budgets applies unchanged. What is new sits above it — three protocols multiplexed on one link, and a coherence model that lets a device and a host share memory rather than copy it.
| Sub-protocol | What it carries | Why it exists |
|---|---|---|
| CXL.io | Discovery, configuration, interrupts, bulk transfer | Essentially PCIe. Every CXL link has it, and a device falls back to it if CXL mode is not negotiated |
| CXL.cache | A device coherently caching the host's memory | Lets an accelerator or NIC work on host data with no explicit copy and no software-managed coherence |
| CXL.mem | The host reading and writing memory attached to the device | Lets memory live behind the link and still be addressed as memory — the capacity tier above |
Type 1 devices have a coherent cache but no memory of their own (a smart NIC); type 2 have both (an accelerator); type 3 use CXL.mem alone (a memory expander). Later revisions widened the topology around them — switching and memory pooling across hosts, then multi-level fabrics, peer-to-peer traffic and genuine sharing of a region between hosts with hardware coherence. The destination is a rack where processors, memory and accelerators are provisioned separately rather than bolted together in fixed ratios.
Because it moves a serial link onto the critical path of a load instruction, and so changes the currency the physical layer is paid in. A switch tolerates the ~100 ns a strong FEC costs; a processor stalled on a cache miss cannot hide any of it. That one fact propagates all the way down: it is why PCIe 6.0 pairs a deliberately weak FEC with CRC and link-level retry rather than Ethernet's Reed–Solomon code, why flit framing exists, why the latency-optimised variant splits its check so the first part of a flit can be forwarded before the whole is verified, and why retimer hops are constrained in a way a network path's are not.
It also puts the PAM4 decision in an uncomfortable light. CXL 3.0 moves to the 64 GT/s physical layer — four-level signalling, and the 9.5 dB penalty of slide 11 — landing on a link where the usual way of buying that margin back is forbidden. You cannot spend latency here. The margin has to come from a shorter channel, a better board, fewer connectors or a lower-noise receiver: which is to say, from the table on slide 10, read with one column deleted.
For all of that, the structure of the problem has not changed since 10GBASE-KR. There is a channel you cannot alter, a pulse response that describes it completely, a set of filters whose taps are the solution of a quadratic minimisation, and a budget that decides whether the result works. Everything in this deck transfers; only the numbers move.
| Quantity | This channel | What it tells you |
|---|---|---|
| Insertion loss at Nyquist | −33.3 dB | The headline difficulty. Beyond about −30 dB, NRZ needs every block on slide 06 |
| Cursor, unequalised | 0.199 | Fraction of the transmitted amplitude arriving on time |
| Worst-case eye, unequalised | −0.87 | Negative means some data patterns invert the decision |
| Noise enhancement of a 9-tap Rx FFE | 0.75 dB | The price of each linear tap — compare a DFE tap, which is free |
| Cursor at the slicer | 12.9 mV | Out of 800 mV launched |
| Total noise | 2.15 mV rms | Dominated by crosstalk, not by residual ISI |
| Q-factor and margin | 6.01, −1.36 dB | Communications Q, not resonator Q. Short of $10^{-12}$; slide 10 prices what recovers it |
| PAM4 penalty | 9.54 dB | Structural, not recoverable by equalisation |
1. Get the S-parameters and check them: passive, causal, reciprocal, correctly de-embedded, mixed-mode port map the right way round. 2. Look for structural damage — a via stub notch near Nyquist, a connector resonance, an unterminated branch — because no equaliser fixes a notch. 3. Compute the pulse response and read the cursor and the first few pre- and post-cursors; that tells you which blocks you need before you design any of them. 4. Build the budget and find out what actually dominates. Only then choose the equalisation — and re-check the budget afterwards, because the equaliser you added changed the noise as well as the signal.
Deck 03 of the Matrix Methods in Engineering series. Companions: Network Parameters (S, Z, Y) and Digital Filter Design.
Single-page HTML · KaTeX-rendered maths · no build step. Source on GitHub · long-form PDF