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Modern SoC Design Presentation Series

Packaging · Interconnects · Memory · Silicon Implementation

Interactive slide decks covering modern System-on-Chip design end-to-end — from advanced packaging and chiplet architectures through memory hierarchies, on-chip interconnects, and silicon implementation. Click any presentation below to launch it.

01

Modern SoC Packaging

Wire bond · Flip-chip · Fan-out · 2.5D CoWoS & EMIB · 3D stacking · Chiplets · UCIe · Thermal & power delivery

30 slides ▶ Launch
02

On-Chip Interconnect & NoC Design

Bus vs crossbar · AXI/ACE · CHI · Network-on-Chip topologies · Coherency protocols · QoS & arbitration

31 slides ▶ Launch
03

Memory Hierarchy in ML Accelerator SoCs

SRAM bitcells · Cache design · DRAM fundamentals · DDR5 · LPDDR5/6 · GDDR7 · HBM3/3E/4 · CXL memory

23 slides ▶ Launch
04

High-Speed SerDes & I/O

PCIe 5/6 · UCIe PHY · PAM4 signaling · CDR · Equalization · Die-to-die links · Co-packaged optics

23 slides ▶ Launch
05

AI / ML Accelerator Architectures

Roofline model · Systolic arrays · Dataflow engines · Sparsity · Mixed precision · NPU integration · Transformer accelerators · H100 & TPU case studies

22 slides ▶ Launch
06

SoCs for ML Inference

Training vs inference · Quantisation (INT8/INT4/FP8) · KV-cache · NPU micro-architecture · On-device LLMs · Speculative decoding · TinyML · Groq LPU & H100 case studies

24 slides ▶ Launch
07

Security in SoC Design

Hardware root of trust · Secure boot · TrustZone & RME · Side-channel attacks & countermeasures · PUFs · TRNG · Crypto accelerators · Memory encryption · Remote attestation · Supply-chain security

22 slides ▶ Launch
08

CXL in ML Accelerator SoCs

CXL.io · CXL.cache · CXL.mem · Memory pooling · Fabric switches · Type 1/2/3 devices · SoC integration

22 slides ▶ Launch
09

Modern ML Accelerator SoC Power Delivery

BSPDN · PIVR · On-die voltage regulation · PDN impedance · eDTC · Power integrity · IR drop

22 slides ▶ Launch
10

Modern SoC Verification

RTL simulation · Formal verification · Emulation · FPGA prototyping · UVM · DFT · Coverage closure

23 slides ▶ Launch
11

Power Management in ML Accelerator SoCs

DVFS · Power domains · PMICs · LDO vs switching regulators · Dark silicon · Power gating strategies

23 slides ▶ Launch
12

Thermal Management in ML Accelerator SoCs

Thermal design power · Direct liquid cooling · Vapour chambers · TIM materials · Throttling · Hotspot mitigation

23 slides ▶ Launch
13

Clocks and Resets in ML Accelerator SoCs

PLL design · Clock distribution · Clock domain crossing · GALS · Reset sequencing · Jitter budgets

23 slides ▶ Launch
14

Modern Trends in FPGA Technology

Advanced nodes · Heterogeneous SoCs · Chiplets · HBM · AI/ML inference · HLS · Partial reconfiguration · Open-source toolchains

23 slides ▶ Launch
15

AMD / Xilinx FPGA Technology & Products

Virtex UltraScale+ · Zynq MPSoC · RFSoC · Versal AI Core/Edge/Premium · Vivado · Vitis · Alveo · Strategic direction

23 slides ▶ Launch
16

FPGAs in Finance

Ultra-low latency trading · Market data parsing · Order book construction · FPGA network stacks · Risk analytics · Vendor ecosystem · Future directions

23 slides ▶ Launch