Interactive slide decks covering the Arm Cortex-M family end-to-end — from the history of Arm itself through the Armv6-M / v7-M / v8-M architectures, the exception model, memory system, DSP & Helium extensions, debug infrastructure, and TrustZone security. Designed as interview preparation for embedded and silicon engineers. Click any presentation below to launch it.
Acorn · ARM1 (1985) · Apple JV · ARM7TDMI · Thumb & Thumb-2 · Armv1 → Armv9 · Profile split · Cortex-M timeline · Corporate history
Cortex-M family (M0–M85) · Armv6-M / v7-M / v8-M · Thumb-2 ISA · Registers · Thread/Handler modes · MSP/PSP · IT blocks · Endianness
Exception model · Vector table · NVIC · Priority & grouping · Tail-chaining · Late arrival · Lazy stacking · WIC · Fault handlers
Memory map · Bit-banding · Memory types & attributes · Ordering barriers · v7-M & v8-M MPU · Caches (M7/M55/M85) · TCM
DSP SIMD extension · Saturating arithmetic · FPv4-SP · FPv5 · Helium vector extension · CMSIS-DSP · Half-precision
SWD/JTAG · DAP · Breakpoints & watchpoints · ITM · DWT · ETM · TPIU · MTB · Semihosting · SEGGER RTT
Sleep / Deep-Sleep · WFI / WFE / SEV · SLEEPONEXIT · WIC · SEVONPEND · Tickless RTOS · ULPMark · Wake-up latency
Secure / Non-Secure state · SAU & IDAU · SG / BXNS / BLXNS · Veneer tables · Secure fault handling · PSA / TF-M