Interactive slide decks covering the Arm Cortex-A application-profile family end-to-end — from the ARM11 classic cores through the AArch64 transition of Cortex-A57, into the Armv9-A flagship Cortex-X925. Designed for SoC, microarchitecture, and kernel engineers working on Arm application processors. Click any presentation below to launch it.
ARM11 · Cortex-A8 · A9 · A15 & big.LITTLE · A53/A57 AArch64 pivot · A72 – A78 · Cortex-X1 – X925 · A510/A520/A715/A720/A725 · DynamIQ
Exception Levels EL0 – EL3 · AArch64 & AArch32 states · A64 ISA · SPSR/ELR/VBAR · Synchronous vs async exceptions · Armv9-A additions
VMSAv8-64 · 4K/16K/64K granules · Stage 1 & Stage 2 · TLB with ASID/VMID · L1–L3–SLC · PoU vs PoC · DMB/DSB/ISB · LDAR/STLR · LSE atomics
NEON (128-bit fixed) · SVE (vector-length agnostic, 128–2048 bit) · SVE2 mandatory in Armv9-A · SME matrix tiles & streaming mode · Fujitsu A64FX
EL2 hypervisor · VHE · EL3 & TrustZone-A · PAC (QARMA) · BTI · MTE colour tags · RME / CCA · Realms · GPT · Four-world model
OoO pipelines · Branch prediction · big.LITTLE → DynamIQ Shared Unit · 1+3+4 layout · PMU · SPE · ETE / TRBE · Speculative side-channel mitigations