PWM · PFM · Constant On-Time & Beyond
Brendan Lynskey · 2025
A DC-DC converter is a switched-mode power supply that transfers energy from input to output through periodic switching. Without a feedback control loop, the output voltage drifts with line, load, and temperature changes.
The choice of control technique determines the fundamental tradeoff between transient response speed, output ripple, efficiency at light load, EMI spectrum, and design complexity. There is no single best technique — only the best fit for your application constraints.
The synchronous buck is the workhorse topology for step-down conversion. All three major control techniques — PWM, PFM, and COT — are applied to this fundamental circuit.
Synchronous buck converter with feedback control loop — the platform for all techniques covered in this presentation
Before diving into specific techniques, the first architectural decision is whether the control loop senses only the output voltage (voltage-mode) or also senses the inductor current (current-mode).
Industry trend: Current-mode control dominates modern integrated DC-DC converters due to simpler compensation, built-in current protection, and superior line transient response. Most PWM controllers from TI, Analog Devices, and MPS use peak current-mode or a COT variant.
PWM is the most established control technique. The switching frequency is fixed; the duty cycle (on-time / period) is modulated to regulate the output.
For a buck converter: VOUT = D × VIN where D is the duty cycle. The controller adjusts D by comparing the error amplifier output to a periodic ramp signal. When the error signal is high, D increases, delivering more energy to the output.
Adjust the duty cycle and observe how the gate drive, inductor current, and output ripple change.
The most popular CMC variant. The inductor current is compared to the error amplifier output (VCOMP). When the sensed current reaches VCOMP, the high-side FET turns off.
At D > 50%, a small perturbation in the inductor current grows on alternate cycles, causing the duty cycle to alternate between two values. This is fixed by adding an artificial ramp (slope compensation) to the sensed current signal.
The compensating ramp slope must be at least 50% of the inductor current down-slope: ma ≥ ½ × m2 where m2 = (VOUT) / L. Insufficient compensation leads to jitter; excessive compensation makes the loop behave like voltage-mode.
| Method | Pros | Cons |
|---|---|---|
| Sense resistor | Accurate, linear | Power loss (I²R) |
| FET RDS(on) | Lossless, no extra parts | Temp-dependent, noisy |
| DCR sensing | Lossless, uses existing L | Requires matched RC network |
The inverse of peak CMC — the off-time is fixed by a clock, and the low-side FET conducts until the inductor current falls to the VCOMP threshold, at which point QHS turns on.
Instead of comparing the peak or valley of the current, a second integrating amplifier (current error amplifier) regulates the average inductor current to match VCOMP.
Design guideline: Peak CMC is the default choice for most buck converters. Use valley CMC for boost or high-duty-cycle applications. Use average CMC when accurate current regulation is the primary requirement (LED constant-current drivers, battery chargers, PFC).
PFM addresses the fundamental weakness of fixed-frequency PWM: poor efficiency at light loads. Instead of switching at a constant frequency, PFM delivers energy pulses only when needed.
The converter monitors VOUT. When it falls below a threshold, one or more switching pulses are delivered to recharge the output capacitor. Between pulses, the converter is essentially idle — no switching losses.
At very light loads, switching losses dominate. PFM reduces the effective switching frequency in proportion to load current, keeping efficiency above 80-90% even at microamp loads. This is critical for battery-powered devices in standby.
PWM oscillator runs continuously but gate drive pulses are skipped when the inductor current would reverse (DCM boundary). Simple to implement — many converters do this automatically.
The controller delivers a burst of several PWM pulses, then enters a sleep state until VOUT droops. Reduces quiescent current to the microamp range. Used in TPS62xxx, LTC3xxx families.
Drag the load current slider to see how efficiency changes. PFM maintains high efficiency at light loads where PWM efficiency collapses.
The simplest form of voltage regulation — no error amplifier, no compensator, no oscillator. The output voltage is compared against upper and lower thresholds, and the switch is toggled accordingly.
Pure hysteretic control is rare in discrete designs but lives on inside integrated converters (TPS6208x, MAX17xxx) and has evolved into the more refined COT architecture. It remains popular for ultra-low-power applications where simplicity and quiescent current are paramount.
COT is a ripple-based control technique that combines the fast transient response of hysteretic control with more predictable frequency behaviour. It has become the dominant architecture for point-of-load (PoL) converters.
There is no error amplifier in the main loop — only a comparator. Comparator response is typically 30-100 ns vs microseconds for an error amp loop. This gives COT near-instantaneous load transient response.
COT needs output voltage ripple in phase with inductor current for stable operation. If the ESR ripple is too small (as with ceramic output capacitors), the converter can experience jitter or multi-pulsing.
This is the central challenge of COT design: modern applications use low-ESR MLCC capacitors that produce minimal resistive ripple. Solutions include emulated ripple injection circuits and advanced architectures like D-CAP.
Relies on the ESR of the output capacitor to generate in-phase ripple at the feedback node. Works well with electrolytic or OS-CON capacitors (ESR > 10 mΩ). Simple and fast, but not usable with all-ceramic output stages.
Example: LM5145, early TPS54xxx
An internal ramp generator synthesises a signal that mimics the inductor current ripple. This artificial ripple is injected into the feedback comparator, allowing COT to work with any output capacitor type including all-MLCC.
Example: TPS543xxx, AOZ2xxx
Uses an internal time-constant matching network to generate emulated ripple. D-CAP requires minimal external components — only the feedback resistor divider. Very fast load transient. Sensitive to board layout.
Example: TPS51xxx, TPS53xxx
D-CAP2 adds a second internal network for improved accuracy with all-ceramic outputs and better jitter performance. D-CAP3 adds a full internal voltage reference and compensation, eliminating external feedback resistors entirely. Targets the simplest possible PoL design.
Example: TPS548xx (D-CAP2), TPS543B20 (D-CAP3)
Adjust VIN and observe how COT maintains a near-constant on-time while the off-time (and thus frequency) adapts. The duty cycle self-adjusts to regulate VOUT.
| Criterion | VM-PWM | Peak CMC-PWM | PFM / Burst | Hysteretic | COT |
|---|---|---|---|---|---|
| Switching freq | Fixed | Fixed | Variable (low) | Variable | Pseudo-fixed |
| Transient response | Slow | Medium | Slow (mode change) | Fastest | Very fast |
| Light-load efficiency | Poor | Poor | Excellent | Good | Good (with PFM) |
| EMI predictability | Best | Good | Poor | Poor | Good |
| Output ripple | Low | Low | Higher (burst) | Set by hysteresis | Low |
| Compensation | Type III | Type II + slope | Minimal | None | None / minimal |
| Design complexity | High | Medium | Low | Low | Low–Medium |
| Ceramic cap support | Yes | Yes | Yes | ESR-dependent | Variant-dependent |
High current (20-100 A), tight transient spec, all-ceramic outputs.
Best fit: COT (D-CAP2/3) or peak CMC with fast error amp. Multi-phase interleaving common.
Ultra-low quiescent current, wide VIN range (single cell Li-ion), months on a coin cell.
Best fit: PFM / burst mode with automatic PWM crossover at higher loads.
Wide VIN (4-42 V), strict EMI (CISPR 25), high reliability, AEC-Q100.
Best fit: Fixed-frequency CMC-PWM with spread-spectrum clocking and external sync.
Sub-1V output, extreme transient requirements (di/dt > 100 A/µs), tight ripple.
Best fit: Multi-phase COT with adaptive on-time. Intel SVID / AMD SVI3 interfaces.
Modern converters are hybrid: Most production ICs implement a PWM/PFM auto-switching architecture — PWM at medium-to-heavy loads for low ripple and predictable EMI, transitioning to PFM or burst mode at light loads for efficiency. The lines between categories are increasingly blurred.
Click to apply a load step and compare how different control techniques respond. Observe overshoot, undershoot, and recovery time.
Digital control replaces the analogue error amplifier and compensator with an ADC, digital compensator (typically a PID implemented in an FPGA or DSP), and a digital PWM (DPWM) module.
Digital control is standard in server VRMs (Intel VR14, AMD SVI3), telecom rectifiers, and solar inverters. Products from Infineon (XDPS21xx), TI (UCD3138), and Renesas (ISL689xx) implement fully digital multi-phase controllers.
Extends COT by dynamically adjusting TON based on VIN and VOUT measurements in real time, rather than using a fixed timer. Maintains tighter frequency regulation across wider operating ranges.
Used in MPS MP28xx, TI TPS543xxx
Deliberately modulates the switching frequency (typically ±5-10%) to spread EMI energy across a wider bandwidth, reducing peak conducted and radiated emissions. Essential for automotive CISPR 25 compliance.
Standard in automotive-grade converters
Uses a mathematical model of the converter to predict future output behaviour and compute the optimal control action one or more steps ahead. Achieves near-deadbeat transient response — settles in 1-2 switching cycles.
Research / high-end FPGA implementations
A derivative of hysteretic control that uses VOUT directly (rather than the error signal) as the ramp. Extremely fast — the output capacitor ESR provides the ramp. Used in some VRM controllers.
ON Semi NCP302x, Renesas ISL95xxx
Reinforcement learning and neural networks used to auto-tune compensator coefficients, predict load transients, and optimise efficiency maps. Still largely in research, but showing promise for complex multi-domain power systems.
Research: ETH Zurich, CPES Virginia Tech
Magnetically coupled inductors, trans-inductor voltage regulators (TLVR), and non-coupled loop (NCL) architectures improve transient response 3–5× beyond discrete inductors. See dedicated slide for CL / TLVR / NCL comparison.
Server VRMs: Infineon, Renesas, MPS
For PWM controllers with error amplifiers, the compensator shapes the loop gain to achieve adequate phase margin (> 45°) and gain margin (> 10 dB) for stable operation.
One zero, one pole (plus the origin pole from the integrator). Provides up to 90° of phase boost. Sufficient for current-mode control where the power stage has a single-pole response.
Two zeros, two poles (plus origin). Provides up to 180° of phase boost. Required for voltage-mode control where the LC filter introduces a resonant double pole with 180° phase drop.
COT and hysteretic controllers skip this entirely — their ripple-based comparator architecture is inherently stable without external compensation networks.
The choice of control technique directly impacts the EMI signature of the converter, which determines filter size and regulatory compliance.
| Technique | EMI Approach |
|---|---|
| PWM | Input LC filter tuned to fSW; shielded inductor |
| PWM + SS | Spread spectrum ±6%; relaxes filter Q requirement |
| PFM | Wideband filtering; may need common-mode choke |
| COT | Near-fixed fSW enables standard filter; PCB layout critical |
| Hysteretic | Most challenging; requires careful shielding + filtering |
Automotive EMI (CISPR 25 Class 5): Fixed-frequency PWM with spread-spectrum clocking is the standard approach. Variable-frequency techniques require significantly more EMI engineering effort.
High-current applications (CPU VRMs, server PoL) use multiple interleaved converter phases to share current, reduce ripple, and improve transient response. The control technique must support phase interleaving.
At light loads, inactive phases are disabled to reduce switching and gate-drive losses. The controller dynamically adjusts the number of active phases based on load current — maintaining efficiency across the full range.
| Technique | Multi-phase support |
|---|---|
| PWM (VM/CMC) | Excellent — master clock distributes phase-shifted triggers |
| COT | Good — phase interleaving via timed offsets; D-CAP2/3 support it natively |
| Hysteretic | Difficult — no common clock reference; phases can clash |
| PFM | Moderate — phase shedding straightforward; interleaving complex |
State of the art: Server VRMs now use 6-12 phase digital multi-phase controllers (Infineon XDPS2222, Renesas ISL69260) with per-phase current balancing, auto phase shedding, and PMBus telemetry.
In multi-phase converters, the choice of magnetic structure profoundly affects transient response, ripple, efficiency, and power density. Three architectures dominate modern VRM design.
Two or more phase windings share a single magnetic core with inverse coupling (dots opposite). The leakage inductance sets the per-phase ripple current, while the mutual inductance appears only during transients.
Würth WE-MCRI, Coilcraft MPI series, Cyntec coupled modules
A hybrid topology patented by Intel for server VRMs. Each phase has its own discrete inductor, but a secondary winding on each core is connected in a series loop across all phases — creating magnetic coupling without a shared core.
Intel VR14/VR15 spec, Infineon XDPE192C3B designs
A further evolution that eliminates magnetic coupling entirely. Each phase inductor has a secondary winding, but the loop is routed so that phase currents sum to zero in the secondary — providing transient current sharing without the frequency-dependent losses of TLVR.
MPS MP2857/MP2971 reference designs, research: CPES Virginia Tech
Evolution path: Discrete inductors → Coupled inductors (CL) → TLVR → NCL. Each step trades magnetic complexity for improved transient performance. Modern AI-class VRMs (>500 A) increasingly use TLVR or NCL to meet sub-microsecond load-step specifications.
Modern AI GPUs and custom accelerators (NVIDIA H100/B200, Google TPU, AMD Instinct) present extreme power delivery challenges that push control techniques to their limits.
Dominant in NVIDIA reference designs. Infineon XDPE192C3B, MPS MP2857 — fast transient response with digital tuning via PMBus. Emulated ripple eliminates ESR dependence.
Two-stage: 48 V → 6–8 V (LLC/resonant) → core (multi-phase buck). Single-stage: Vicor Factorised Power, Infineon hybrid DC-DC, or sigma converters eliminate the intermediate bus entirely.
Workload-aware controllers pre-position inductor current before a load step using GPU telemetry. Intel SVID 3.0 and NVIDIA GPU-to-VRM signalling reduce undershoot by 30–50% vs reactive control.
Industry trend: The 48 V power architecture endorsed by the Open Compute Project (OCP) is now standard in AI data centres, driving demand for high-ratio converters with >95% peak efficiency at 1000+ W.
GaN FETs switch at 5-10 MHz with minimal losses, enabling smaller passives and faster transients. Control loops must keep up — ADC/comparator speeds become the bottleneck. COT and digital control are best positioned for multi-MHz operation.
The trend toward integrating FETs, controller, inductor, and passives in a single package (e.g., TI LMZM33xxx, MPS MPM3xxx) is driving control architectures toward zero-external-component designs — D-CAP3 and similar are ideal.
Data centre power is moving from 12V to 48V distribution. Converters like the Vicor NBM, Infineon hybrid LLC, and TI TLVM series use new topologies (sigma, switched-capacitor, hybrid) that require hybrid control combining resonant and PWM techniques.
FPGA-based controllers with on-chip system identification can measure the plant transfer function in real-time and auto-tune compensation. Digital twin models running alongside the converter enable predictive maintenance and lifetime estimation.
The convergence thesis: Future converters will blur all boundaries — digital controllers running hybrid PWM/COT algorithms with AI-assisted tuning on GaN power stages, all in a single package. The winner is whoever integrates best, not who has the best single technique.
Erickson & Maksimović, Fundamentals of Power Electronics, 3rd ed. · Ridley, Power Supply Design, Vol. 1-3 · TI SLVA057, Understanding and Applying Current-Mode Control Theory · TI SLVA281, Voltage Mode vs Current Mode · NPTEL, Switched Mode Power Conversion (course)
Brendan Lynskey · 2025 · Educational use