Modern SoC Design · Part 15

AMD / Xilinx
FPGA Technology & Products

From Virtex to Versal — Architecture, Ecosystem & Strategic Direction

23 Slides · Deep Dive

00

Agenda

Heritage & Organization

  • Xilinx Heritage & AMD Acquisition
  • Adaptive Computing Division

UltraScale+ Families

  • Virtex UltraScale+ Deep Dive
  • Kintex UltraScale+ & Artix
  • Zynq UltraScale+ MPSoC
  • Zynq RFSoC

Versal Platform

  • Versal Architecture Overview
  • Versal AI Core Series
  • Versal AI Edge Series
  • Versal Premium Series
  • Versal HBM & Gen 2 Roadmap

Design Tools

  • Vivado Design Suite
  • Vitis Unified Platform
  • Vitis AI

Markets & Applications

  • Data Center & Alveo
  • 5G & Communications
  • Automotive (XA)
  • Aerospace & Defense

Competition & Outlook

  • vs Intel Agilex / Lattice Nexus
  • Strategic Direction & Roadmap
01

Xilinx Heritage & AMD Acquisition

Key Milestones

  • 1985 — Xilinx founded; invented the FPGA (XC2064)
  • 1998 — Virtex family: first modern FPGA with block RAM & DLLs
  • 2004 — Virtex-4: first column-based architecture
  • 2010 — Virtex-7: 28 nm, 2M logic cells, first 2.5D interposer (SSI)
  • 2015 — UltraScale+ at 16 nm FinFET+, UltraRAM introduced
  • 2018 — Versal ACAP announced — FPGA + AI Engines + ARM SoC
  • 2020 — AMD announces $49B all-stock acquisition of Xilinx
  • 2022 — Acquisition closes Feb 14; Xilinx becomes AMD Adaptive Computing

Strategic Rationale

AMD sought heterogeneous compute across CPU + GPU + FPGA + AI. Xilinx delivered:

  • 40+ years of programmable logic IP
  • Dominant share in Telecom, Aerospace, Automotive
  • Versal ACAP as the future adaptive platform
  • ~8,500 patents in reconfigurable computing

Acquisition Economics

  • $49B all-stock deal (1.7234 AMD shares per Xilinx share)
  • Xilinx FY2022 revenue: ~$3.7B
  • 35x trailing P/E — premium for strategic positioning
  • Expected $300M+ annual synergies by Year 3
02

AMD Adaptive Computing Division

Organization & Revenue

  • Reports as Embedded segment alongside embedded processors
  • Quarterly revenue ~$1.5B (FY2023), significant decline from Xilinx peak due to inventory digestion
  • Headed by VP/GM of Adaptive & Embedded Computing Group
  • Engineering centers: San Jose, Dublin, Hyderabad, Singapore, Beijing

Revenue Mix by End Market

  • Communications — ~35% (5G RAN, wireline)
  • Data Center — ~20% (Alveo, SmartNIC)
  • Automotive / ISM — ~20% (ADAS, industrial)
  • A&D — ~15% (radar, EW, space)
  • Other — ~10% (broadcast, consumer, test)

Product Portfolio Overview

FamilyNodeCategory
Artix-7 / UltraScale+28/16 nmCost-Optimized FPGA
Kintex-7 / UltraScale+28/16 nmMid-Range FPGA
Virtex-7 / UltraScale+28/16 nmHigh-Performance FPGA
Zynq-700028 nmSoC (A9 + FPGA)
Zynq UltraScale+ MPSoC16 nmSoC (A53/R5 + FPGA)
Zynq UltraScale+ RFSoC16 nmSoC + RF-ADC/DAC
Versal (AI Core/Edge/Premium/HBM)7 nmACAP
Versal Gen 2TSMC N6Next-gen ACAP (AI Edge/Prime/Premium, sampling 2025–26)
Spartan UltraScale+ (SU10P/SU25P/SU35P)16 nm FinFET+Cost-Optimized FPGA (2024)
03

Virtex UltraScale+ Architecture Deep Dive

Fabric Architecture (16 nm FinFET+)

  • CLB: 8 six-input LUTs + 16 flip-flops per slice; 2 slices/CLB
  • LUTs optionally split as 2x 5-input or used as 64-bit distributed RAM / shift register
  • UltraRAM: 288 Kb dual-port SRAM blocks; cascade-chaining to build multi-MB on-chip buffers
  • Block RAM: 36 Kb true dual-port; configurable as 2x 18 Kb
  • Up to 4.4M system logic cells (VU19P — largest monolithic FPGA)

DSP48E2 Slice

  • 27x18 signed multiplier + 48-bit accumulator
  • Pre-adder for symmetric FIR filter optimization
  • Up to 12,288 DSP slices (VU13P)
  • 891 MHz Fmax — ~21.8 TMAC/s peak INT8

GT Transceivers

  • GTY: up to 32.75 Gb/s NRZ per lane
  • GTM (VU27P/VU29P): 58G PAM4, 112G with FEC
  • Up to 120 GTY transceivers per device
  • Support for PCIe Gen3/Gen4, 100GbE, Interlaken, JESD204C

HBM Variants (VU35P / VU37P / VU45P / VU47P)

  • HBM2 stacks integrated via 2.5D CoWoS interposer
  • VU37P: 2x HBM2 stacks = 8 GB, 460 GB/s
  • VU47P: 2x HBM2 stacks = 16 GB, 460 GB/s
  • 32 pseudo-channels; AXI3 interface per channel
  • Key for financial tick-to-trade, genomics, network analytics
04

Kintex UltraScale+ & Artix Families

Kintex UltraScale+ — Mid-Range Champion

  • 16 nm FinFET+; optimized price/performance/watt
  • Up to 1.1M logic cells (KU19P)
  • Up to 128 GTY transceivers @ 32.75 Gb/s
  • 2,160 DSP48E2 slices; up to 48 MB UltraRAM
  • Integrated PCIe Gen3 x16 & Gen4 x8 hard blocks
  • Integrated 100G Ethernet MAC + PCS

Target: Wireless infrastructure, video, medical imaging, test & measurement

Key Kintex Devices

DeviceLCsBRAM (Mb)DSPGTY
KU3P356K221,36816
KU5P523K361,82432
KU15P1,045K751,96832

Artix UltraScale+ — Cost-Optimized

  • 16 nm; lowest power in UltraScale+ family
  • Up to 352K logic cells (AU25P)
  • GTH transceivers @ 16.3 Gb/s (lower cost serdes)
  • No UltraRAM; Block RAM only (~11 Mb max)
  • Hardened PCIe Gen3 x8
  • I/O banks support DDR4 up to 2,400 MT/s

Target: Motor control, sensor fusion, protocol bridging, industrial IoT, low-cost video

Artix-7 (28 nm) — Still In Production

  • Lowest cost Xilinx FPGA; <$10 BOM at volume
  • Up to 215K logic cells; GTP transceivers @ 6.6 Gb/s
  • 1.0V core; total device power often <1 W
  • Automotive-grade XA variants available
  • Widely used in legacy designs, expected in production through 2030+
05

Zynq UltraScale+ MPSoC

Processing System (PS)

  • APU: Quad-core ARM Cortex-A53 @ 1.5 GHz, 32KB L1I/D + 1 MB shared L2
  • RPU: Dual-core ARM Cortex-R5F @ 600 MHz, lockstep or split mode, TCMs
  • GPU: ARM Mali-400 MP2 (EG/EV variants)
  • PMU: MicroBlaze-based Platform Management Unit — boot, power domains, isolation
  • CSU: Configuration Security Unit — RSA-4096 auth, AES-256 encryption, secure boot chain

PS-PL Interfaces

  • AXI HPM: 2x 128-bit high-performance master ports (PS→PL)
  • AXI HPC: 2x 128-bit high-performance coherent slave ports (PL→PS, cache-coherent)
  • AXI HP: 4x 128-bit high-performance slave ports (PL→DDR)
  • AXI LPD: Low-power domain port for RPU-centric traffic
  • Aggregate PS-PL bandwidth: >100 GB/s

Security & Isolation

  • ARM TrustZone on A53 — secure/non-secure worlds
  • XMPU: Xilinx Memory Protection Unit — region-based access control
  • XPPU: Xilinx Peripheral Protection Unit — per-peripheral access gating
  • Hardware root of trust with eFUSE-based key storage
  • Anti-tamper & DPA-resistant AES engine

Variants

VariantPL LCsFeature
ZU2–ZU5 (CG)103–256KCost-optimized
ZU5–ZU9 (EG)256–600K+ GPU + Video Codec
ZU7–ZU19 (EV)504–1.1M+ H.264/H.265 VCU

EV variants include hardened H.264/H.265 Video Codec Unit — 4K60 encode/decode

06

Zynq UltraScale+ RFSoC

Direct RF Sampling Architecture

  • Integrates RF-ADCs (up to 14-bit, 5 GSPS) and RF-DACs (up to 14-bit, 10 GSPS) on-die
  • Eliminates external mixer/IF stages — direct RF-to-digital
  • Up to 16 ADC + 16 DAC channels per device
  • Integrated digital down/up-converters (DDC/DUC) with NCOs
  • On-chip PLL for multi-tile synchronization (MTS)

Generational Evolution

GenADC RateDAC RateKey Improvement
Gen 1 (ZU27/28/29DR)4.096 GSPS6.554 GSPSFirst direct RF FPGA SoC
Gen 2 (ZU47/48/49DR)5.0 GSPS9.85 GSPSHigher BW, better SFDR
Gen 3 (ZU65/67DR)5.0 GSPS10.0 GSPSMore tiles, SD-FEC hard IP
DFE (ZU21/25/27)5.0 GSPS10.0 GSPSHardened DFE for 5G NR

DFE Variant — 5G Optimized

  • Hardened Digital Front End (DFE) blocks replace soft logic
  • DFE includes: CFR (crest factor reduction), DPD (digital pre-distortion), mixers, filters
  • Saves ~50% PL resources vs soft DFE implementation
  • Enables 200 MHz IBW per antenna for 5G NR FR1
  • Integrated SD-FEC (LDPC/Turbo) hard blocks for channel coding

Target Applications

  • 5G Massive MIMO — direct RF eliminates per-antenna RF chains
  • Phased Array Radar — multi-channel coherent beamforming
  • Electronic Warfare — wideband spectrum sensing & jamming
  • SIGINT / ELINT — instantaneous bandwidth to 4+ GHz
  • Spectrum Monitoring — multi-GHz real-time analysis
  • Cable / Satellite — multi-carrier modem consolidation
07

Versal ACAP Architecture Overview

Network-on-Chip (NoC) — AXI Interconnect Scalar Engines Dual ARM Cortex-A72 Dual ARM Cortex-R5F Platform Mgmt Controller OCM · GIC · L2 Cache Security: Crypto, RoT, PUF Boot: QSPI, SD, JTAG Adaptable Engines FPGA Fabric (CLBs) Block RAM · UltraRAM DSP58 Engines GTY / GTYP Transceivers PCIe Gen4/5 · MRMAC DDR4/LPDDR4 Controllers Intelligent Engines AI Engine Array VLIW + SIMD Cores 32 KB Tile Local Memory Cascade Stream Routing Up to 400 AI Engine Tiles ~130 INT8 TOPS (AI Core) I/O & Memory DDR4/LPDDR4 DDRMC · XPIO · HDIO · GTY/GTYP/GTM · PCIe Gen4/5 · MRMAC 400G Platform Management Controller (PMC) Boot · Configuration · Security · Power Management · Debug · Health Monitoring

ACAP = Adaptive Compute Acceleration Platform

Versal is not just an FPGA — it is a heterogeneous SoC with three distinct compute domains connected by a programmable NoC.

NoC Architecture

  • Hardened AXI streaming NoC replaces soft interconnect
  • Deterministic, QoS-aware routing with configurable arbitration
  • Eliminates ~40% of fabric congestion from interconnect logic
  • 128-bit data paths @ 1 GHz = 16 GB/s per port

Key Differentiators vs UltraScale+

  • 7 nm TSMC vs 16 nm — 2x density, 40% lower power
  • AI Engines: dedicated vector DSP array (not in UltraScale+)
  • Hardened NoC replaces soft AXI interconnect
  • Hardened DDR memory controllers (DDRMC)
  • New DSP58: 27x24 multiplier (vs DSP48E2 27x18)
08

Versal AI Core Series

AI Engine Tile Architecture

  • Each tile: VLIW scalar core + 512-bit SIMD vector unit
  • Vector unit: 8x INT8 MACs/cycle or 16x INT4 MACs/cycle or 8x FP32 operations
  • 32 KB local data memory + 16 KB program memory per tile
  • Tiles interconnected via cascade streaming — direct neighbor data transfer with no NoC overhead
  • AXI4-Stream interfaces to PL fabric for data ingress/egress
  • Each tile runs at 1.0–1.25 GHz

AI Core Device Lineup

DeviceAI EnginesLUTsDSP58INT8 TOPS
VC1502128337K928~50
VC1702192477K1,312~75
VC1902400900K1,968~133
VC28024001.96M3,984~133

Dataflow Programming Model

  • AI Engine graphs are expressed as directed acyclic graphs (DAGs) in C/C++
  • Compiler maps kernels to tiles and routes streams automatically
  • Data flows through cascade chains without returning to main memory
  • Achieves >80% compute utilization for well-structured workloads
  • Suits: CNN inference, 5G L1 (FFT, LDPC), beamforming, radar signal processing

AI Core vs GPU Inference

  • VC1902 delivers ~133 INT8 TOPS at 75 W — competitive with NVIDIA T4 (130 TOPS @ 70 W)
  • Advantage: deterministic latency — no batching requirement
  • Advantage: PL-accelerated pre/post-processing integrated on-chip
  • Advantage: inline deployment (SmartNIC, 5G) without host CPU
  • Disadvantage: smaller software ecosystem, longer development cycle
09

Versal AI Edge Series

Power-Efficient Edge AI

  • AI Engine-ML tiles: optimized for INT4/INT8 inference at lower power
  • AI Engine-ML adds native sparse matrix support (2:4 structured sparsity) — effectively 2x throughput for pruned models
  • Up to 304 AI Engine-ML tiles (VE2802)
  • Peak: ~200 INT4 TOPS at sub-40W total device power
  • Integrated H.264/H.265 VCU in select variants

AI Edge Device Lineup

DeviceAI-ML TilesLUTsPeak INT8
VE175232295K~16 TOPS
VE210264440K~32 TOPS
VE2302152671K~75 TOPS
VE28023041.02M~150 TOPS

Automotive ADAS Use Cases

  • Multi-sensor fusion: camera, lidar, radar processed on single device
  • CNN-based object detection (YOLO, SSD) at <10 ms latency
  • Functional safety: lockstep R5F, ECC memory, built-in self-test
  • AEC-Q100 qualified variants (XA prefix)

Other Edge Applications

  • Robotics: real-time motor control + vision AI on one device
  • Surveillance: multi-stream video analytics, person re-ID
  • Medical: ultrasound beam-forming + AI-assisted diagnosis
  • Industrial: defect detection, predictive maintenance on production line
  • Drone/UAV: obstacle avoidance + payload processing
10

Versal Premium Series

Highest Bandwidth Versal

  • Designed for data center networking, wired telecom, test & measurement
  • 112G PAM4 GTM transceivers — up to 72 lanes per device
  • Integrated 600G Ethernet subsystem (DCMAC — dual 300G or 6x100G)
  • Integrated PCIe Gen5 x32 with CCIX support
  • Up to 1.97M LUTs, 4,000+ DSP58 engines

Crypto & Security

  • Hardened multi-100G inline crypto engines (AES-256-GCM, IPsec/MACsec)
  • Up to 600 Gbps aggregate crypto throughput — no fabric resources consumed
  • FIPS 140-3 ready; PQC (post-quantum crypto) via PL soft implementation
  • Integrated hardware root of trust, PUF, secure boot

Premium Device Lineup

DeviceLUTsGTM (112G)DCMACPCIe
VP1052586K326x100GGen5 x16
VP1202833K442x DCMAC2x Gen5
VP14021.15M562x DCMAC2x Gen5
VP18021.97M723x DCMAC3x Gen5

Target Workloads

  • 400G/800G switches & routers — packet processing + programmable forwarding
  • 5G UPF / BNG — user-plane function acceleration
  • Network test equipment — multi-rate protocol exerciser
  • Financial exchanges — ultra-low-latency matching engines with 100G connectivity
  • Storage controllers — NVMe-oF, erasure coding, compression
11

Versal HBM Series

HBM2e Integration

  • Up to 2x HBM2e stacks on 2.5D CoWoS interposer
  • 32 GB total HBM2e capacity (16 GB per stack)
  • Aggregate bandwidth: 820 GB/s (32 pseudo-channels x ~25.6 GB/s each)
  • AXI-based memory controller; configurable QoS per channel
  • Both AI Engines and PL fabric have direct NoC paths to HBM

Why HBM on an FPGA?

  • Eliminates external DDR memory bottleneck — many acceleration workloads are memory-bound
  • Pin-count savings: HBM uses thousands of micro-bumps on interposer vs hundreds of DDR pins
  • Lower power per bit: ~3.9 pJ/bit vs ~8 pJ/bit for DDR4
  • Enables in-memory compute patterns without external DRAM latency

HBM Device Lineup

DeviceAI EnginesHBMBWLUTs
VH15221288 GB410 GB/s587K
VH154212816 GB410 GB/s587K
VH158219216 GB820 GB/s929K
VH174230432 GB820 GB/s1.97M
VH178240032 GB820 GB/s1.97M

Acceleration Workloads

  • Genomics: Smith-Waterman alignment, variant calling — large reference genome in HBM
  • Financial risk: Monte Carlo simulation with massive state tables
  • Network analytics: deep packet inspection with regex at line rate
  • Database acceleration: in-memory joins, Bloom filters, hash tables
  • Graph analytics: random-access graph traversal benefits from HBM bandwidth
12

Versal Gen 2 & Next-Gen Roadmap

Versal Gen 2 (Announced 2024)

  • Migrates to advanced TSMC N6 (6 nm) process node (Versal Premium Gen 2 confirmed); AI Edge / Prime Gen 2 on the same N6 family
  • AI Engine v2 (AIE2): enhanced vector ISA, BFloat16 native support, higher MAC density
  • Expected 2–3x AI TOPS/W improvement over Gen 1
  • Updated ARM Cortex-A78 (or newer) scalar engines
  • Enhanced NoC v2 with higher throughput and lower latency
  • Up to 128 Gbps PAM4 transceivers (Gen 1 was 112G); 32/56/72 lanes per device for 800G / 1.6T Ethernet

Known Product Lines

  • Versal Gen 2 AI Edge: targeting automotive L2+ ADAS and robotics
  • Versal Gen 2 Prime: general-purpose replacement for UltraScale+ designs
  • Versal Gen 2 Premium: 800G–1.6T networking
  • AI Edge Gen 2 & Prime Gen 2 sampling as of mid-2025; Versal Premium Gen 2 silicon samples H1 2026, production shipments H2 2026

Architecture Trends

  • Chiplet integration: AMD exploring UCIe-based multi-die FPGA architectures leveraging AMD's chiplet expertise from EPYC
  • CXL 3.x support for shared memory pools with host CPUs (CXL 3.2 Dec 2024; CXL 4.0 Nov 2025 on PCIe 7.0)
  • Coherent interconnect between FPGA fabric and CPU complex
  • Deeper AMD CDNA/RDNA IP integration possibilities
  • Software-defined approach: more heterogeneous hard blocks, fewer soft implementations

Migration Considerations

  • Versal Gen 2 is not pin-compatible with Gen 1 — board redesign required
  • Vivado → Vitis Unified IDE migration: design flow consolidation
  • IP core compatibility maintained via Vitis libraries abstraction
  • AI Engine kernel C/C++ source generally portable between AIE v1 → v2
  • FPGA fabric RTL designs: largely portable with re-synthesis
13

Vivado Design Suite

Core Design Flow

  • Synthesis: Vivado Synthesis (XST replacement) — supports VHDL-2008, SystemVerilog-2012 subset
  • Implementation: opt_design → place_design → phys_opt_design → route_design
  • Timing Closure: integrated STA engine; timing-driven place & route with incremental compilation
  • Report-based methodology: report_timing_summary, report_methodology, report_drc
  • Generates .bit (bitstream) and .xsa (hardware handoff to Vitis)

IP Integrator (IPI) Block Design

  • Graphical block diagram editor for IP assembly
  • Connection automation: infers AXI interconnects, clocking, resets
  • Address map editor for memory-mapped peripherals
  • BD validation catches connectivity/parameter mismatches
  • Supports Zynq PS block, Versal CIPS block as anchor IPs
  • Platform design workflow: export extensible platforms (.xpfm) for Vitis acceleration

Advanced Features

  • Incremental Compile: reuse prior placement — reduces iteration time by 2–5x for small ECOs
  • Abstract Shell: partition designs for team-based IP assembly (DFX / partial reconfiguration)
  • Block-level synthesis: out-of-context (OOC) runs for modular compilation
  • Tcl scripting: entire flow scriptable; write_checkpoint / read_checkpoint for state save/restore

Vivado ML (Machine Learning-Optimized)

  • Introduced in Vivado 2021.1+ — ML-based placement & routing algorithms
  • ML strategy: automatically selects optimization directives based on design characteristics
  • Claims ~10% WNS improvement and 2x faster timing closure for congested designs
  • Integrated design analysis: congestion heatmaps, utilization density, timing path histogram
14

Vitis Unified Software Platform

Vitis HLS (High-Level Synthesis)

  • C/C++ → RTL synthesis with pragma-driven micro-architecture control
  • Key pragmas: #pragma HLS PIPELINE, #pragma HLS UNROLL, #pragma HLS ARRAY_PARTITION, #pragma HLS DATAFLOW
  • Supports AXI4 master/slave, AXI4-Stream, and AXI4-Lite interface synthesis
  • Generates co-simulation testbench; RTL-C co-sim for functional verification
  • Iteration time: minutes (HLS) vs days (manual RTL)

Vitis Libraries

  • Open-source, performance-optimized HLS libraries on GitHub
  • BLAS: matrix multiply, solver, decomposition
  • DSP: FFT, FIR, DDS, mixer
  • Data Analytics: regex, Bloom filter, sort, group-by
  • Vision: OpenCV-equivalent accelerated functions
  • Codec: gzip, zstd, snappy compression/decompression
  • Graph: PageRank, shortest path, triangle count

AI Engine Compiler & Simulation

  • AI Engine graphs written in C/C++ with AIE API
  • aiecompiler: maps kernels to tiles, schedules, routes streams
  • aiesimulator: cycle-accurate simulation of AI Engine array
  • x86simulator: fast functional simulation on host
  • Performance profiling: cycle counts, stalls, memory conflicts, stream throughput

XRT Runtime & Acceleration Workflow

  • XRT (Xilinx Runtime): open-source host runtime for Alveo / embedded
  • OpenCL & XRT native API for host-device communication
  • Kernel execution: xclbin binary loaded at runtime
  • Flow: C++ kernel → HLS → .xo → v++ linker → .xclbin
  • Hardware emulation: full RTL sim via Vivado XSIM behind XRT abstraction
  • Supports PCIe-attached (Alveo) and embedded (Zynq/Versal) targets
15

Vitis AI

DPU IP — Deep Learning Processing Unit

  • Configurable soft DPU instantiated in FPGA fabric (Zynq/Versal PL)
  • Architectures: DPUCZDX8G (Zynq), DPUCVDX8G (Versal AI Core), DPUCV2DX8G (Versal AI Edge)
  • Configurable parallelism: B512, B1024, B2048, B4096 — trade fabric area for throughput
  • Supports Conv2D, DepthwiseConv, Deconv, Pooling, Eltwise, Softmax, etc.
  • Multi-DPU deployment: instantiate 2–4 DPUs for multi-model parallel inference

Quantization & Optimization

  • Vitis AI Quantizer: post-training quantization (PTQ) from FP32 → INT8
  • Quantization-aware training (QAT) via PyTorch/TensorFlow plugins
  • Calibration: requires representative dataset (~100–1000 images)
  • Typical accuracy loss: <1% top-5 for well-conditioned models
  • Pruning support: structured channel pruning for further compression

Framework Support & Model Zoo

  • Compiles models from PyTorch, TensorFlow 2.x, ONNX Runtime
  • Vitis AI Compiler: vai_c_xir → XIR graph intermediate representation → DPU instructions
  • Model Zoo: 200+ pre-optimized models (ResNet, YOLO, EfficientNet, PointPillars, Transformer variants)
  • Custom op support via CPU subgraph fallback or PL-based custom kernels

Edge vs Cloud Deployment

AspectEdge (Zynq/Versal)Cloud (Alveo)
Power5–30 W75–225 W
Throughput~50–300 FPS (ResNet-50)~1000–5000 FPS
Latency<5 ms single image<2 ms batched
RuntimeVitis AI Runtime (VART)VART + XRT
OSPetaLinux / bare-metalUbuntu + XRT driver
16

AMD FPGA in Data Centers — Alveo

Alveo Accelerator Card Portfolio

CardFPGAMemoryNetworkForm
U25NXCU25DDR42x 25G SFP28OCP SmartNIC
U55CXCU55C (HBM)16GB HBM22x QSFP28PCIe x16
U250XCU2504x 16GB DDR42x QSFP28PCIe x16
V70Versal AI Core 7 nm (XVC2802)16 GB DDR4—PCIe Gen4, HH/HL, 75 W
V80Versal Premium VP180232 GB HBM2e (820 GB/s) + DDR44x 200G (via 2x QSFP-DD)PCIe Gen4/Gen5

SmartNIC / DPU Use Cases

  • U25N: OVS offload, vSwitch, IPSEC, load balancing
  • AMD Pensando competitor — FPGA-based infrastructure processing
  • Deployed at Microsoft Azure (Project Catapult / Brainwave heritage)
  • SNAP framework: standardized NIC abstraction for FPGA SmartNICs

Cloud FPGA Instances

  • AWS F2 (Dec 2024): up to 8× Virtex UltraScale+ HBM VU47P (16 GB HBM/FPGA) — 60% better $/perf than F1
  • AWS F1 (legacy): VU9P-based (f1.2xlarge → f1.16xlarge)
  • Alibaba Cloud: F3 instances with VU9P
  • Nimbix / AMD Developer Cloud: Alveo U250/U55C on demand
  • Use: genomics, financial simulation, video transcoding, database acceleration

V80 — Next-Gen Data Center Card

  • Based on Versal HBM series — AI Engines + HBM2e
  • 32 GB HBM2e, 820 GB/s bandwidth
  • PCIe Gen5 x16 host interface
  • 200G networking (2x QSFP-DD)
  • Targets: LLM serving pre/post-processing, RAG pipeline acceleration, genomics
  • Successor to U55C — major generational leap with AI Engine compute
17

AMD FPGA in 5G & Communications

5G RAN Architecture Role

  • RFSoC dominates the Radio Unit (O-RU): direct RF sampling replaces discrete RF chains
  • Versal AI Core targets the Distributed Unit (O-DU): L1 physical layer processing
  • L1 functions: FFT/IFFT, LDPC encode/decode, MIMO equalization, beamforming, PRACH detection
  • AMD claims >60% share of 5G RAN FPGA sockets globally

O-RAN Integration

  • RFSoC DFE aligns with O-RAN 7.2x split — processing split between O-RU and O-DU
  • eCPRI / IEEE 1914.3 fronthaul interface natively supported
  • T-Cell reference design: 4T4R to 32T32R massive MIMO configurations
  • AMD provides complete L1 IP for O-DU on Versal (partnered with Ericsson, Nokia, Samsung)

Massive MIMO & Beamforming

  • 64T64R: requires 64 RF chains — RFSoC consolidates from 8+ boards to 1–2
  • Beamforming matrix: 64×12 subcarrier groups × per-symbol = massive compute
  • AI Engines excel at complex matrix multiply — natural fit for beamweight calculation
  • DPD (Digital Pre-Distortion): per-antenna DPD runs in RFSoC DFE hard blocks

Wireline & Transport

  • Versal Premium for optical transport: OTN, FlexO, 400G/800G coherent DSP assist
  • Kintex UltraScale+ in access equipment: GPON, XGS-PON, 25G-PON OLT
  • Cable infrastructure: DOCSIS 3.1/4.0 CMTS acceleration
  • Satellite ground stations: DVB-S2X modulation, multi-carrier processing
  • Timing: IEEE 1588 PTP hardware timestamping with sub-ns accuracy
18

AMD FPGA in Automotive

XA (Xilinx Automotive) Family

  • XA Artix / Kintex / Zynq UltraScale+: AEC-Q100 Grade 2 (–40 to +105 °C)
  • XA Versal AI Edge: next-gen automotive ADAS platform
  • Extended qualification: 15+ year supply commitment, PPAP documentation
  • Dedicated automotive support team with APQP, 8D problem-solving
  • Zero-defect program: DPPM <1 target

ADAS Sensor Fusion

  • Camera: ISP pipeline + CNN object detection on single Zynq/Versal
  • Lidar: point cloud processing, 3D object detection (PointPillars)
  • Radar: FFT-based range-Doppler processing, CFAR detection
  • Fusion layer: multi-modal object tracking, prediction, path planning
  • Single XA Versal AI Edge can process 8+ cameras + 1 lidar + 4 radars simultaneously

Functional Safety (ISO 26262)

  • XA devices support up to ASIL-D decomposition (ASIL-B/C natively)
  • Lockstep R5F in Zynq/Versal: dual-core comparison for ASIL-D safety island
  • Soft Error Mitigation (SEM) IP: detects & corrects SEUs in configuration memory
  • Safety manual and FMEDA (Failure Mode Effects & Diagnostic Analysis) provided
  • Built-in self-test (BIST) for fabric, BRAM, UltraRAM

Other Automotive Uses

  • Display bridge: MIPI/LVDS transcoding, AR HUD rendering
  • In-vehicle networking: TSN switch, 10BASE-T1S gateway
  • EV powertrain: motor control FOC, BMS monitoring
  • V2X communication: C-V2X / DSRC protocol processing
  • OTA update: FPGA partial reconfiguration enables field-updateable hardware functions
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AMD FPGA in Aerospace & Defense

Radiation-Tolerant & Space-Grade

  • RT (Radiation Tolerant): Kintex UltraScale XQRKU060 — total ionizing dose (TID) >100 krad(Si)
  • Space-grade: extended testing for SEL (Single Event Latchup) immunity >80 MeV·cm²/mg
  • SEU mitigation via built-in CRAM scrubbing + ECC on BRAM
  • QML-Q/-V qualification per MIL-PRF-38535
  • Heritage in 200+ space missions (GPS, LEO constellations, deep space probes)

Radar & Electronic Warfare

  • AESA radar: real-time pulse compression, MTI, STAP processing
  • EW / SIGINT: wideband digital receivers, real-time spectral analysis, threat identification
  • RFSoC enables direct digitization of RF signals up to ~4 GHz
  • Multi-channel coherent systems: RFSoC MTS for phase-aligned sampling
  • AI-assisted threat classification using Versal AI Engine inference

SOSA & Open Architecture Standards

  • SOSA (Sensor Open Systems Architecture): modular C4ISR standard
  • AMD FPGAs core to SOSA-aligned 3U/6U VPX processing cards
  • VITA 49.2 (VITA Radio Transport) for standardized IF/RF data streaming
  • Partners: Curtiss-Wright, Mercury (Andover), L3Harris, BAE Systems
  • Key enabler: partial reconfiguration for mission-adaptable waveforms

A&D Specific Considerations

  • ITAR/EAR compliance: AMD provides US-manufactured variants for classified programs
  • Anti-tamper: bitstream encryption (AES-256), authentication (RSA-4096), DPA countermeasures
  • Obsolescence management: 15–20 year lifecycles; last-time-buy programs
  • Trusted foundry: select devices available through DMEA-accredited sources
  • Extended temperature: military (–55 to +125 °C) and industrial (–40 to +100 °C) grades
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Competitive Positioning vs Intel & Lattice

DimensionAMD (Xilinx)Intel (Altera)Lattice
High-EndVersal (7nm)Agilex 7/9 (7/5nm)N/A
Mid-RangeKintex US+ (16nm)Agilex 5 (EMIB)N/A
Low-PowerArtix (28/16nm)Cyclone V / 10Nexus (28nm FD-SOI)
SoCZynq US+ / VersalAgilex SoC (A53/A76)—
AI EnginesAI Engine (VLIW+SIMD)AI Tensor BlockssensAI (soft)
RF IntegrationRFSoC (ADC/DAC)——
HBMVirtex HBM / Versal HBMAgilex 9 HBM (planned)—
Top Serdes112G PAM4 (GTM)116G PAM412.5G
Market Share~51%~35%~8%
Tool SuiteVivado / VitisQuartus / OneAPIRadiant / Propel

AMD Strengths

  • RFSoC: no competitor in integrated RF FPGA
  • Versal AI Engine: most mature hardened AI array in FPGA
  • Ecosystem: largest FPGA IP/tool ecosystem (Vivado maturity)
  • CPU+GPU+FPGA: unique heterogeneous portfolio post-merger
  • 5G dominance: >60% of RAN FPGA sockets

AMD Weaknesses / Intel Advantages

  • Intel Agilex 9 on Intel 7/4 process — competitive at high-end
  • Intel Quartus timing closure often faster for large designs
  • Intel HPS (Hard Processor System) with Cortex-A76 — newer core than AMD A72
  • Lattice dominates ultra-low-power edge (<100 mW) niche
  • AMD Vivado license cost remains a barrier for small teams
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Strategic Direction & Outlook

AMD's Adaptive Computing Roadmap

  • Versal Gen 2 (sampling 2025, volume 2026): TSMC N6, AIE v2 (BF16, FP8, INT4), up to 128 Gbps PAM4, CXL 2.0 with path to CXL 3.x
  • Versal Gen 3 (horizon): 3 nm, deeper CPU integration, chiplet-based
  • Long-term: UCIe chiplet interconnect — FPGA fabric dies mixed with CPU/GPU/HBM dies
  • Embedded roadmap convergence: Versal replaces UltraScale+ over 3–5 year transition

Convergence with CPU & GPU

  • AMD uniquely possesses x86 (Zen), GPU (CDNA/RDNA), and FPGA (Versal)
  • Chiplet vision: Zen core complex + FPGA fabric on same package via AMD Infinity Fabric
  • CXL 3.x / 4.0: coherent memory sharing between FPGA and CPU — no DMA copies
  • Potential: EPYC + Versal combo chip for inline acceleration (SmartNIC, storage, AI)

AI-Everywhere Thesis

  • Every AMD product line gains AI capability: Ryzen AI, Instinct, Versal AI
  • FPGA AI niche: deterministic, inline, low-batch inference where GPUs are overkill
  • Vitis AI + ONNX Runtime EP: unified deployment across CPU/GPU/FPGA targets
  • AI Engine roadmap: more INT4/FP8 support, transformer-optimized ISA extensions
  • Edge AI consolidation: Versal AI Edge displaces discrete NPU + FPGA combinations

Key Challenges Ahead

  • Software gap: CUDA ecosystem dwarfs Vitis — developer adoption remains #1 challenge
  • Intel competition: Agilex 9 / 3 aggressive on process node and features
  • Revenue diversification: Comms segment cyclicality (5G capex slowdown)
  • Design complexity: Versal ACAP learning curve steeper than pure FPGA
  • ASIC erosion: Broadcom, Marvell ASIC alternatives in high-volume networking