Modern SoC Design - 13

Clocks & Resets in
ML Accelerator SoCs

PLL design · Clock distribution · Clock domain crossing · GALS architectures · Reset sequencing · Jitter budgets

22 slides Modern SoC Design Series
Motivation
01

Why Clocks & Resets Matter

3+ GHzTypical ML accelerator core frequency
~40%ECO spins attributed to clock/reset issues
<1 psJitter budget for 112G SerDes reference clocks

Timing Closure at GHz Frequencies

  • At 3 GHz, a clock period is ~333 ps — setup margin of 30–50 ps leaves zero room for clock uncertainty
  • Clock skew across a 600 mm² die can exceed 100 ps without careful CTS
  • Process variation (PVT corners) adds 15–25% frequency uncertainty; must be budgeted in clock planning
  • Multi-billion transistor designs have 50–200+ clock domains, each with unique frequency and phase requirements
  • Clock-related failures are the #1 cause of silicon re-spins in complex SoCs

Impact on ML Workloads

  • HBM PHY — 2.4 GT/s per pin requires <3 ps RMS jitter on the transmit clock
  • SerDes (PCIe 6.0) — 64 GT/s PAM4 demands sub-picosecond reference clock jitter
  • Systolic arrays — thousands of MACs sharing a clock tree; 1 ps of skew = incorrect accumulation
  • DVFS — dynamic frequency scaling for power efficiency requires seamless clock switching under load
  • Improper reset sequencing can corrupt weight memory, break coherency, or brick PLL lock-up

Modern ML accelerators like NVIDIA H100 have 10+ independent clock domains with frequencies spanning 30 MHz (management) to 2.1+ GHz (SM cores), each requiring independent PLL, distribution tree, and reset sequencing.

Section I
02

Clock Generation

PLL architectures, specifications, and advanced clocking techniques for multi-GHz ML accelerator SoCs.

Reference Osc
→
PFD
→
Charge Pump
→
Loop Filter
→
VCO
→
Output Divider
→
Clk Out
Feedback Divider (/N) closes the loop from output back to PFD
Clock Generation
03

PLL Architecture

The charge-pump PLL is the workhorse of SoC clock generation, converting a low-frequency crystal reference (typically 25–100 MHz) into GHz-range domain clocks.

Charge-Pump PLL Block Diagram

  • Phase-Frequency Detector (PFD) — compares reference and feedback edges; generates UP/DOWN pulses proportional to phase error
  • Charge Pump (CP) — converts PFD pulses into current; typical ICP = 50–500 μA; matching UP/DN currents critical for spur reduction
  • Loop Filter (LPF) — 2nd/3rd order RC filter; sets loop bandwidth (typically fref/10 to fref/20); determines lock time and jitter peaking
  • VCO — LC-tank (GHz) or ring oscillator (lower area); KVCO = 200–800 MHz/V; typical phase noise −110 dBc/Hz @ 1 MHz offset
  • Feedback Divider (/N) — programmable integer or fractional; fout = fref × N/M; determines output frequency granularity

Loop Bandwidth Trade-offs

  • Wide BW (>1 MHz) — fast lock (<5 μs), tracks reference noise, suppresses VCO noise
  • Narrow BW (<100 kHz) — slow lock (>50 μs), filters reference noise, exposes VCO noise
  • Optimal BW: crossover point where reference and VCO noise contributions are equal

Lock Time

  • Frequency acquisition: 2–5 μs (aided by frequency detector)
  • Phase lock: 5–20 μs for analog PLL
  • Settling to <1 ps jitter: 50–200 μs
  • Critical for DVFS: must re-lock within voltage transition window
Clock Generation
04

Advanced PLL Types

All-Digital PLL (ADPLL)

  • Replaces analog charge pump + VCO with TDC + digital loop filter + DCO
  • Time-to-Digital Converter (TDC): ~5 ps resolution using inverter delay chains
  • Digitally Controlled Oscillator (DCO): varactor bank with thermometer-coded tuning
  • Fully synthesizable, portable across process nodes; dominates in FinFET designs
  • Intel/AMD use ADPLLs extensively for core clock generation in 5 nm and below

Fractional-N PLL

  • Achieves non-integer frequency ratios via delta-sigma modulator dithering the divider ratio
  • Frequency resolution: fref / 224 (sub-Hz with 100 MHz reference)
  • Quantization noise shaped out of band by 3rd-order MASH modulator
  • Enables fine-grained DVFS steps (e.g., 1 MHz granularity at 2+ GHz)
  • Spur cancellation via DAC-based charge pump compensation

Bang-Bang PLL (BBPLL)

  • Uses binary phase detector (Alexander or Hogge) — outputs only early/late
  • Inherently nonlinear; analyzed via describing function or Markov chain models
  • Dominates in SerDes CDR at 56, 112 and 224 Gbps
  • Jitter tolerance vs. jitter transfer trade-off set by loop gain proportional/integral paths

Sub-Picosecond Jitter PLLs

  • State-of-art: <50 fs RMS integrated jitter (12 kHz–20 MHz)
  • LC-tank VCO with tail-current filtering and flicker noise reduction
  • Injection-locked oscillators achieve <100 fs by leveraging reference edge timing
  • Required for 224G-PAM4 SerDes (deployed in NVIDIA NVLink 5 / Blackwell, 2024) and HBM4 PHY interfaces (JEDEC JESD270-4, 2025; 8 Gbps/pin, 2 TB/s per stack)
Clock Generation
05

PLL Specifications & Comparison

Key PLL metrics that determine suitability for different clock domains in an ML accelerator SoC.

Parameter Analog CP-PLL ADPLL Frac-N PLL BBPLL (CDR)
RMS Jitter (integ.) 200–500 fs 300–800 fs 150–400 fs 100–300 fs
Phase Noise @ 1 MHz −110 dBc/Hz −100 dBc/Hz −112 dBc/Hz −108 dBc/Hz
Lock Time 5–20 μs 1–10 μs 10–50 μs N/A (tracking)
Freq. Range 0.5–4 GHz 0.2–6 GHz 0.5–5 GHz 10–60 GHz
Power 3–8 mW 1–5 mW 5–15 mW 10–30 mW
Area (5 nm) 0.02–0.05 mm² 0.005–0.02 mm² 0.03–0.08 mm² 0.01–0.04 mm²
Portability Poor Excellent Moderate Moderate
Use Case Core clocks Core + DVFS Fine-grained DVFS SerDes CDR
A modern ML accelerator SoC (e.g., H100, Gaudi 3, TPU v5) typically instantiates 10–30 PLLs: 2–4 for compute cores (ADPLL, DVFS-capable), 4–8 for HBM/DDR PHYs (low-jitter fractional-N), 4–12 for SerDes lanes (BBPLL CDR), and 1–2 for management/always-on domains.
Section II
06

Clock Distribution

Getting a clean clock edge from PLL output to billions of flip-flops with minimal skew, jitter, and power overhead.

<30 psTarget global clock skew (5 nm)
~30%Dynamic power consumed by clock network
106+Clock buffers in a large ML SoC
Clock Distribution
07

Clock Tree Synthesis

Topologies

  • H-Tree — symmetric binary-branching tree; inherently balanced; used for global clock spines; O(N) wire length
  • Mesh / Grid — interconnected grid shorts all leaf nodes; lowest skew (<5 ps) but highest power; used for critical clock domains
  • Fishbone / Spine — central trunk with lateral branches; good skew/power trade-off; most common in ASIC CTS
  • Hybrid — mesh at top level, trees at cluster level — NVIDIA Hopper uses this for SM clock distribution

Useful Skew

  • Intentionally skewing clock arrival at specific endpoints to fix setup/hold violations
  • CTS tools (Innovus, ICC2) support useful-skew optimization: can recover 5–15% frequency
  • Must not violate hold timing on any path — hold fix requires delay insertion

CTS Goals & Constraints

  • Skew: <30 ps global, <10 ps local (within cluster)
  • Insertion delay: 200–500 ps from PLL output to leaf flip-flop
  • Transition time: <80 ps at leaf to avoid short-circuit power
  • Buffer sizing: graded drive strengths (16x → 8x → 4x → 2x)
  • NDR (Non-Default Rules): double-width, double-spacing for clock nets to reduce coupling noise
  • Shielding: ground wires flanking clock routes to reduce cross-talk induced jitter

OCV & AOCV Derating

  • On-Chip Variation (OCV) derating: 5–10% on clock path delays
  • Advanced OCV (AOCV) uses statistical depth-based derating — less pessimistic
  • POCV (Parametric OCV): per-cell sigma values for sign-off accuracy
Clock Distribution
08

Clock Mesh & Spine Architecture

Global Clock Mesh

  • Metal grid (M10–M12) driven by multiple pre-drivers from the PLL
  • Self-averaging: any single buffer failure does not create hot-spot skew
  • Achieves <5 ps skew across full die at cost of 2–3× power vs. tree
  • Used for the most critical domain: NPU core clock in ML accelerators

Clock Grid Shielding

  • VSS shield wires on both sides of clock routes
  • Reduces coupling-induced jitter by 60–80%
  • 3× routing resource cost; justified only for <10 critical clocks

Capacitive Loading

  • Typical ML core clock: 2–5 nF total load
  • At 2 GHz, Pclk = C × V² × f = 5 nF × 0.75² × 2G ≈ 5.6 W per domain
  • Clock gating is essential — see slide 10
Clock Distribution
09

Clock Gating

Clock gating eliminates switching activity on idle logic, saving 25–60% of dynamic power in typical ML accelerators.

ICG Cell (Integrated Clock Gating)

  • Latch-based gating: enable sampled on negative edge, AND-gated with clock on positive edge
  • Prevents glitches — output transitions only when clock is low
  • Standard cell: CKLNQD1 (typical library naming)
  • Insertion by synthesis tools (Design Compiler, Genus) with -clock_gating switch
// Latch-based ICG cell (RTL model)
module icg_cell (
  input  wire clk,
  input  wire enable,
  output wire gated_clk
);
  reg enable_latched;

  // Latch enable on negative clock edge
  always @(*) begin
    if (!clk)
      enable_latched = enable;
  end

  assign gated_clk = clk & enable_latched;
endmodule

Hierarchical Clock Gating

  • Level 0 (leaf): register-level gating; each FF group has own ICG
  • Level 1 (block): functional unit gating; disables entire MAC array, SRAM bank
  • Level 2 (cluster): power domain gating; shuts off full compute cluster clock
  • Level 3 (global): PLL shutdown or bypass to low-freq reference

Clock Gating Efficiency

  • Metric: % of flip-flops gated — target >85% in synthesis
  • ML workloads: high gating efficiency due to bursty compute patterns
  • Sparsity-aware accelerators gate MAC columns when input is zero — 40–70% savings

Enable Timing

  • Enable signal must be stable before rising clock edge
  • Setup time: ~100 ps to ICG latch (process dependent)
  • Multi-cycle enable paths need proper SDC constraints
Section III
10

Clock Domain Crossing

Safely transferring data between asynchronous clock domains — the most error-prone aspect of multi-clock SoC design.

105+CDC crossings in a large ML SoC
1–3Cycle latency penalty per synchronizer
>1015Required MTBF for safe operation (hours)
Clock Domain Crossing
11

CDC Fundamentals — Metastability

Metastability Theory

  • When a flip-flop samples a signal transitioning during its setup/hold window, the output enters a metastable state
  • Resolution time is exponential: P(unresolved after t) = T0 · fclk · fdata · e−t/τ
  • Time constant τ depends on process: ~20–40 ps in 5 nm FinFET
  • A single flip-flop at 2 GHz has MTBF of only seconds — completely insufficient
  • Two-stage synchronizer provides additional resolution time of one full clock period

MTBF Calculation

  • MTBF = e(Tres/τ) / (T0 · fclk · fdata)
  • Tres = available resolution time (clock period minus setup time)
  • 2-FF sync at 2 GHz: MTBF ≈ 1018 hours (>100 billion years)
  • 3-FF sync: MTBF ≈ 1040 hours; used when τ is not well characterized
// Two-Flop Synchronizer
module sync_2ff #(
  parameter WIDTH = 1
)(
  input  wire             clk_dst,
  input  wire             rst_n,
  input  wire [WIDTH-1:0] data_in,
  output wire [WIDTH-1:0] data_out
);
  reg [WIDTH-1:0] sync_ff1, sync_ff2;

  always @(posedge clk_dst or negedge rst_n) begin
    if (!rst_n) begin
      sync_ff1 <= '0;
      sync_ff2 <= '0;
    end else begin
      sync_ff1 <= data_in;
      sync_ff2 <= sync_ff1;
    end
  end

  assign data_out = sync_ff2;

  // Synthesis attributes
  // synopsys sync_set_reset "rst_n"
  (* dont_touch = "true" *)
  (* async_reg = "true" *)
endmodule

Synchronization Latency

  • 2-FF: 1.5–2 destination clock cycles latency
  • 3-FF: 2.5–3 cycles — use for high-frequency destinations
  • Latency is the cost of safety; cannot be avoided
Clock Domain Crossing
12

CDC Data Transfer Techniques

Single-Bit Crossing

  • 2-FF synchronizer — for level signals; 2 cycles latency
  • Toggle synchronizer — for pulses; sender toggles on pulse, receiver detects toggle change after 2-FF sync
  • Pulse synchronizer — converts pulse to level, syncs, re-converts; handles pulse-to-pulse minimum spacing

Multi-Bit Crossing

  • Gray-code FIFO — gold standard for streaming data; pointers encoded in Gray code cross domains safely
  • MUX recirculation — data held stable in source, select signal synchronized; single-bit control crosses
  • Handshake protocol — REQ/ACK 4-phase; lowest throughput but simplest; good for configuration registers

Async FIFO Design

  • Write pointer (binary) in write clock domain; read pointer (binary) in read domain
  • Gray-coded pointers cross to opposite domain via 2-FF sync
  • Full/empty determined by comparing synced pointers
  • Depth must be power-of-2 for Gray code to work correctly
// Gray-code pointer crossing (async FIFO)
// Write domain: binary write pointer
wire [ADDR_W:0] wr_ptr_bin;
wire [ADDR_W:0] wr_ptr_gray;
assign wr_ptr_gray = wr_ptr_bin ^
                     (wr_ptr_bin >> 1);

// Sync gray write pointer to read domain
reg [ADDR_W:0] wr_ptr_gray_r1, wr_ptr_gray_r2;
always @(posedge rd_clk or negedge rd_rst_n) begin
  if (!rd_rst_n) begin
    wr_ptr_gray_r1 <= '0;
    wr_ptr_gray_r2 <= '0;
  end else begin
    wr_ptr_gray_r1 <= wr_ptr_gray;
    wr_ptr_gray_r2 <= wr_ptr_gray_r1;
  end
end

// FIFO depth calculation:
// depth >= (f_wr/f_rd) * burst_len + 2
//   + synchronization latency margin
Clock Domain Crossing
13

CDC Verification

Static CDC analysis catches structural violations; functional CDC verification ensures data integrity across domains.

Static CDC Analysis Tools

ToolVendorKey Capability
SpyGlass CDCSynopsysStructural + protocol checks
Meridian CDCCadenceFormal + structural hybrid
Questa CDCSiemensAssertion-based CDC
Real Intent AscentReal IntentDeep reconvergence analysis

Reconvergence Detection

  • Two signals from same source crossing to same destination via different synchronizers
  • Can arrive in different order — creates inconsistent state
  • Must be grouped into a single multi-bit crossing (FIFO or handshake)

Structural vs Functional CDC

  • Structural: missing synchronizer, wrong synchronizer type, multi-bit bus without encoding
  • Functional: data coherency, protocol correctness, FIFO overflow/underflow under realistic traffic
  • Structural finds ~80% of CDC bugs; functional CDC needed for remaining 20%
  • Formal CDC proves absence of metastability propagation using model checking

Glitch Detection

  • Combinational logic on CDC path can produce glitches before synchronizer
  • Glitch = spurious transition sampled as valid data change
  • Rule: no combinational logic between source flop and synchronizer first stage
  • CDC tools flag COMBO_LOGIC_ON_CDC_PATH violations
Clock Domain Crossing
14

GALS — Globally Asynchronous, Locally Synchronous

GALS partitions the SoC into independently-clocked synchronous islands communicating through asynchronous interfaces.

Mesochronous

  • Same frequency, unknown phase
  • Simplest: FIFO or phase aligner
  • Used between tiles sharing a PLL but with different distribution delays
  • Example: NVIDIA GPC-to-GPC within same clock domain

Plesiochronous

  • Nearly same frequency (ppm offset)
  • Elastic buffer absorbs frequency difference
  • Used in multi-die systems with independent crystals
  • Example: CXL link between host and accelerator (600 ppm tolerance)

Heterochronous

  • Completely unrelated frequencies
  • Requires full async FIFO or handshake
  • Most common in SoC: NPU @ 2 GHz vs. NoC @ 1 GHz vs. PCIe @ 250 MHz
  • Highest latency penalty but maximum flexibility

Pausable Clocking

  • Clock is stretched (paused) when data is not ready at domain boundary
  • Mutual exclusion element (mutex) arbitrates between clock and handshake request
  • Zero-overhead when data is ready; stalls only on actual conflict
  • Used in ARM Cortex-M series for low-power GALS wrappers

GALS Wrapper Architecture

  • Each synchronous island wrapped with: local clock generator + async FIFO ports + handshake interfaces
  • Port controller handles flow control and data validity signaling
  • Enables per-island DVFS without global frequency coordination
  • Intel Ponte Vecchio uses GALS between its 47 tiles
Section IV
15

Reset Architecture

Designing robust reset networks that bring a multi-domain SoC to a known state safely and in the correct order.

Power-On Reset
→
PLL Lock
→
Always-On Domain
→
Core Domains
→
PHY Init
→
Fabric & IO
→
Boot
Reset Architecture
16

Reset Design Patterns

Synchronous vs Asynchronous Reset

  • Synchronous reset: reset sampled on clock edge; clean timing but requires running clock to take effect
  • Asynchronous reset: resets immediately regardless of clock; but deassertion can cause metastability
  • Industry standard: asynchronous assert, synchronous deassert — best of both worlds
// Async assert, sync deassert reset synchronizer
module reset_sync (
  input  wire clk,
  input  wire async_rst_n,  // from POR
  output wire sync_rst_n    // to logic
);
  reg rst_ff1, rst_ff2;

  always @(posedge clk or negedge async_rst_n) begin
    if (!async_rst_n) begin
      rst_ff1 <= 1'b0;  // async assert
      rst_ff2 <= 1'b0;
    end else begin
      rst_ff1 <= 1'b1;  // sync deassert
      rst_ff2 <= rst_ff1;
    end
  end

  assign sync_rst_n = rst_ff2;
endmodule

Reset Synchronizer Design

  • One reset synchronizer per clock domain — ensures clean deassertion in each domain's timing
  • Reset synchronizer flops placed near PLL output with high-priority routing
  • Must use dedicated reset-sync cells from standard cell library (e.g., RSDFQD1)
  • Recovery/removal timing checks replace setup/hold for async reset paths

Reset Tree Distribution

  • Reset tree is built like a clock tree: balanced buffering for low skew
  • Reset assertion skew is less critical (all flops go to known state)
  • Reset deassertion skew is critical — must arrive at all flops within one clock period
  • CTS tools handle reset tree synthesis with set_ideal_network -no_propagate constraints

Reset Glitch Filtering

  • External reset pins susceptible to noise; require deglitch filter (typically 100 ns–1 μs)
  • Schmitt trigger inputs on reset pads
  • Brown-out detector holds reset during voltage droop
Reset Architecture
17

Reset Sequencing & SoC Reset State Machine

Multi-Domain Reset Ordering

  • Phase 1 — Power-On Reset (POR): asserted when VDD crosses threshold (~0.7 V for 5 nm); held for 10–100 μs until supply stabilizes
  • Phase 2 — PLL Lock: reference clock starts; PLLs begin frequency acquisition; reset held until PLL LOCK indicator asserts (5–200 μs)
  • Phase 3 — Always-On Domain: PMU, RTC, reset controller, OTP — these must be operational before any other domain
  • Phase 4 — Core Domains: NPU cores, SRAM arrays, DMA engines — released in dependency order
  • Phase 5 — PHY Init: HBM PHY, SerDes, DDR PHY — each has internal training sequence post-reset
  • Phase 6 — Fabric & I/O: NoC, PCIe, Ethernet — link training begins after PHY is ready

Warm vs Cold Reset

  • Cold reset: full POR equivalent; all state lost; PLLs re-lock; full boot sequence
  • Warm reset: preserves DRAM content, PLL lock, and always-on domain state; faster recovery (~100 μs vs. ~10 ms)
  • Watchdog timer triggers warm reset on firmware hang; escalates to cold reset after N failures

Reset Sources

  • POR — power-on detection circuit
  • Brown-out — voltage droop detector
  • Watchdog — timer expiry (firmware hang)
  • Software — register write to reset controller
  • Debug — JTAG system reset
  • Thermal — over-temperature shutdown
  • Security — tamper detection trigger

Reset State Machine

  • POR_WAIT → PLL_LOCK → AON_INIT → CORE_INIT → PHY_TRAIN → ACTIVE
  • Timeout watchdog on each phase — escalates to POR on failure
  • Reset cause register captures source for firmware diagnostics
  • SoC reset controller is in always-on domain; survives warm reset
Section V
18

ML Accelerator Specifics

How clocking and reset challenges manifest specifically in large-scale ML accelerator SoCs, with real-world architectures and jitter budgets.

ML Accelerator Specifics
19

Clock Architecture in ML SoCs

A typical ML accelerator has 6–15 major clock domains, each with independent PLL, distribution tree, and DVFS capability.

Clock Domain Typical Freq. PLL Type Jitter Req. DVFS Notes
NPU / SM Core 1.5–2.5 GHz ADPLL / Frac-N <1 ps RMS Yes Boost clocking, per-cluster DVFS
SRAM / L2 Cache 1.0–2.0 GHz ADPLL <2 ps RMS Yes Often ratio-locked to core
NoC / Interconnect 1.0–1.8 GHz ADPLL <3 ps RMS Yes Separate from core for decoupling
HBM PHY 1.2–2.4 GHz Frac-N <1.5 ps RMS Limited Per-stack PLL; training required
PCIe / CXL 100 MHz ref CDR (BBPLL) <0.5 ps RMS No SerDes CDR per lane; 100 MHz refclk
Management CPU 200–500 MHz Integer PLL <10 ps RMS Yes Low-power always-on domain
NVIDIA H100 (GH100): 6 HBM3 stack sites (5 active on SXM5 = 80 GB; H100 NVL enables all 6 for 96 GB HBM3); 132 of 144 SMs enabled on SXM5 with per-GPC boost clocking up to 1980 MHz; NVLink 4.0 at 2×112 Gbps PAM4 per link (900 GB/s aggregate bidirectional), separate PCIe Gen5 refclk domain. Total: ~20+ PLLs on a single 814 mm² die.
ML Accelerator Specifics
20

Jitter Budgets for High-Speed Interfaces

HBM PHY Jitter Allocation

  • HBM3 (6.4 Gbps/pin): 78 ps UI; HBM3E (8–10 Gbps/pin): 100–125 ps UI; HBM4 (8 Gbps/pin × 2048-bit, 2026): 125 ps UI — total jitter budget ~15.6 ps (20% of UI) on HBM3
  • PLL jitter contribution: <1.5 ps RMS (<10 ps pk-pk)
  • DLL jitter for DQS alignment: <2 ps RMS
  • Crosstalk + SSN: ~5 ps deterministic jitter
  • Remaining margin: ~3 ps for silicon aging and temperature variation

DDR5 / LPDDR5 Clock Jitter

  • DDR5-6400: 312 ps UI; clock jitter budget <2.5 ps RMS
  • LPDDR5X-8533: 234 ps UI; tighter <1.8 ps RMS due to WCK-DQS tracking
  • Duty cycle distortion: must be <47/53% for reliable sampling

SerDes Reference Clock

  • PCIe Gen5 (32 GT/s): 100 MHz refclk, <0.5 ps RMS jitter (PCIe CEM spec)
  • PCIe Gen6 (64 GT/s PAM4): <0.3 ps RMS; requires ultra-low-jitter XO + PLL cascade
  • PCIe Gen7 (128 GT/s PAM4, PCI-SIG 2025): <150 fs RMS reference jitter target; doubles Gen6 lane rate
  • 112G Ethernet SerDes: <200 fs RMS reference clock jitter per IEEE 802.3ck
  • 224G PAM4 SerDes (IEEE 802.3dj for 1.6T Ethernet, 2025 baseline): <100 fs RMS target reference jitter
  • NVLink 4.0 (112 Gbps): proprietary spec, estimated <150 fs RMS reference jitter

PLL Cascading & Jitter Accumulation

  • Multi-stage PLL chain: XO → system PLL → per-domain PLL → clock tree
  • Jitter adds as RSS: Jtotal = √(J1² + J2² + ... + Jn²)
  • Each PLL stage contributes 100–300 fs; 3 stages = 170–520 fs total
  • Minimize cascade depth; use direct PLL output where possible for jitter-critical paths
Case Studies
21

Industry Case Studies

NVIDIA H100 / Hopper GPU

  • GPC Boost Clocking: each GPC can boost independently up to 1980 MHz based on thermal headroom and power budget
  • Per-GPC ADPLL with <5 μs frequency transition; voltage regulator follows within 10 μs
  • Clock mesh within each SM; H-tree between SMs in a GPC; global spine for GPC-to-GPC
  • 8 HBM3 stacks, each with dedicated fractional-N PLL at 1.6 GHz (3.2 Gbps/pin)
  • NVLink 4.0: 18 links each with 2×112 Gbps PAM4 lanes (25 GB/s unidirectional per link) = 900 GB/s bidirectional aggregate; BBPLL CDR per lane

AMD MI300X / Infinity Fabric

  • XGMI (Infinity Fabric): 32 GT/s links between 8 XCDs using dedicated reference PLLs with <200 fs jitter
  • Each XCD (chiplet) has independent core PLL; mesochronous interface to Infinity Fabric
  • 8 HBM3 stacks (192 GB total, 24 GB per stack) sitting on 4 base IODs in the 3.5D CoWoS package; separate PLL per HBM channel
  • GALS architecture: each chiplet is a synchronous island; IOD acts as async bridge

Apple M-series SoC

  • Clock domains: P-core (~3.5 GHz), E-core (~2.4 GHz), GPU (~1.4 GHz), Neural Engine (~2 GHz), fabric (~1 GHz), LPDDR5 PHY
  • Aggressive per-cluster DVFS with <1 μs transition time using ADPLL
  • Unified memory architecture means LPDDR5 clock domain serves all IPs — single jitter budget for system memory
  • Always-on SEP (Secure Enclave) domain with independent low-power oscillator

Intel Ponte Vecchio

  • 47 tiles across base + compute + HBM + Xe Link + EMIB bridges
  • Each compute tile has independent PLL; 16 Xe cores per tile at up to 1.6 GHz
  • Xe Link: 8 ports × 16 lanes of 53 Gbps SerDes; CDR PLL per lane
  • Multi-tile reset sequencing managed by base tile — orchestrates power-on of compute tiles in defined order
  • Foveros 3D stacking adds vertical clock distribution challenges; TSV-based clock feeding
References
22

References & Further Reading

Books & Standards

  • Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. — PLL fundamentals ch. 15–16
  • Dally & Poulton, Digital Systems Engineering — synchronization, clock distribution
  • Cummings, Simulation and Synthesis Techniques for Asynchronous FIFO Design (SNUG 2002) — definitive CDC reference
  • JEDEC HBM3 (JESD238A) and HBM4 (JESD270-4, 2025) specs — jitter specs for HBM PHY
  • PCI-SIG PCIe 6.0 spec — reference clock jitter requirements
  • IEEE 802.3ck — 100/200/400 Gbps Ethernet SerDes jitter budgets

Industry Resources

  • Synopsys SpyGlass CDC User Guide — CDC methodology and rule reference
  • Cadence Innovus CTS User Guide — clock tree synthesis techniques
  • NVIDIA GTC talks on Hopper architecture — clock domain and power management details
  • AMD ISSCC papers on Infinity Fabric clocking — multi-die clock distribution
  • Intel Ponte Vecchio Hot Chips 2022 presentation — multi-tile clocking challenges
  • Bjelogrlić et al., Sub-100fs Jitter PLL Design, JSSC 2023

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