MODERN SOC DESIGN · PRESENTATION 12

Thermal Management in
ML Accelerator SoCs

Dissipating 1000W+ from AI Silicon

Thermal design power Direct liquid cooling Vapour chambers TIM materials Throttling Hotspot mitigation

The Thermal Challenge

Power density — modern AI accelerators exceed 1 W/mm² locally; NVIDIA B200 dissipates 1000 W from ~814 mm² of active die area
Junction temperature — T_j,max typically 100–105 °C for datacenter GPUs; every 10 °C rise doubles failure rate (Arrhenius: AF = e^{ΔE_a/k(1/T₁−1/T₂)})
Thermal runaway — leakage current rises exponentially with temperature → positive feedback loop; at 7 nm, leakage is ~30% of total power at T_j = 100 °C
Reliability — electromigration, NBTI, HCI all accelerate with temperature; solder joint fatigue from thermal cycling limits package lifetime to ~60k power cycles

"Thermal management, not transistor density, is the primary limiter of AI accelerator performance scaling."
— TSMC OIP 2024 keynote

Power trend: A100 400 W → H100 700 W → B200 1000 W → B300 1400 W → Rubin VR200 (2026) ~2300 W → Rubin Ultra (2027) ~3600 W

Failure Mechanism	E_a (eV)	AF @ +15 °C
Electromigration	0.7	3.1×
NBTI	0.5	2.2×
TDDB	0.3–0.7	1.7–3.1×
Solder fatigue	—	Coffin-Manson

Section I

Thermal Fundamentals

Conduction · Convection · Radiation · Thermal resistance networks · RC models

Heat Transfer Mechanisms

Three Modes of Heat Transfer

Conduction — Q = kAΔT/L; dominant within die, TIM, heatsink. Silicon k = 130 W/m·K, copper k = 400 W/m·K
Convection — Q = hAΔT; forced air h = 25–250 W/m²·K, liquid h = 500–10,000 W/m²·K
Radiation — Q = εσA(T⁴_s−T⁴_surr); negligible inside server (<2% of total), relevant only for exposed outdoor enclosures

Thermal RC Model

R_th = temperature rise per watt (K/W or °C/W)
C_th = thermal mass (J/K); determines transient response
Time constant τ = R_th × C_th; silicon die τ ≈ 1–10 ms, heatsink τ ≈ 10–100 s

Thermal Resistance Network

Junction (Tj)

↓ R_jc = 0.02–0.10 °C/W

Case / IHS

↓ R_cs = 0.05–0.20 °C/W (TIM2)

Heatsink / Cold Plate

↓ R_sa = 0.05–0.30 °C/W

Ambient (Ta)

T_j = T_a + P × (R_jc + R_cs + R_sa)
For 700 W, R_total must be < 0.10 °C/W to keep ΔT < 70 °C

Thermal Design Power (TDP)

TDP: Maximum sustained power the cooling solution must dissipate; defined by worst-case realistic workload
TDP vs Peak: Actual power can exceed TDP during short bursts (PL2/Tau); NVIDIA H100 SXM: TDP = 700 W, peak > 900 W for ms-scale transients
T_j,max: Maximum junction temperature spec: typically 100–105 °C for datacenter, 125 °C for automotive (AEC-Q100 Grade 1)
T_case,max: IHS/lid temperature limit seen by the cooling solution; H100 specifies T_case ≤ 83 °C
T_ambient: Data center inlet temperature: ASHRAE A1 = 15–32 °C, A2 = 10–35 °C; Google/Meta design for 35 °C inlet

Accelerator	TDP (W)	Die Area	W/mm²
NVIDIA A100	400	826 mm²	0.48
NVIDIA H100 SXM	700	814 mm²	0.86
NVIDIA B200	1000	2×~800 mm² (reticle, NV-HBI)	~0.63
AMD MI300X	750	12 chiplets	~0.65
Intel Gaudi 3	900 (air) / 1200 (liq)	TSMC N5 OAM	—
Google TPU v5e	~250	~400 mm²	~0.63
NVIDIA B300	1400	2×~800 mm²	~0.88
AMD MI355X	1400	CDNA4, TSMC N3	—
NVIDIA Rubin VR200 (2026)	~2300	2×reticle TSMC N3	~1.4

Key insight: TDP is a thermal contract between the chip designer and the cooling solution designer — exceeding it causes thermal throttling or shutdown.

Thermal Interface Materials (TIM)

TIM fills microscopic air gaps between mating surfaces. Without TIM, contact resistance dominates: bare metal-to-metal leaves ~99% of area as air gaps (k_air = 0.025 W/m·K).

TIM1: Die → IHS

Material	k (W/m·K)	BLT (μm)	R_th (°C·mm²/W)
Thermal paste	3–8	25–75	3–25
Indium solder	86	20–50	0.23–0.58
Liquid metal (Ga alloy)	40–73	10–30	0.14–0.75
Graphite sheet	10–15 (through)	100–200	7–20
STIM (solder TIM)	50–86	15–25	0.17–0.50

Intel uses STIM (indium) on server CPUs; NVIDIA uses high-performance paste or STIM depending on SKU.

TIM2: IHS → Heatsink

Thermal paste — most common; 3–12 W/m·K; prone to pump-out (squeeze-out under thermal cycling) and dry-out (volatile loss over months)
Phase-change pads — solid at room temp, melt at 45–55 °C; self-healing on each power cycle; 3–6 W/m·K
Graphite pads — compressible, reusable; in-plane k > 1000 W/m·K but through-plane only 10–15 W/m·K
Liquid metal — gallium-based; 40+ W/m·K; corrosive to aluminium; requires nickel plating on heatsink

Degradation: TIM pump-out increases R_th by 20–50% over 3–5 years in datacenter. STIM eliminates this failure mode entirely.

Section II

Air Cooling

Heatsinks · Vapour chambers · Fan design · Server airflow management

Heatsink Design

Fin Geometry & Materials

Copper baseplate — k = 400 W/m·K; superior spreading but 3.3× heavier and 5× costlier than aluminium
Aluminium fins — k = 205 W/m·K; extruded or bonded-fin construction; 60–80% of datacenter heatsinks
Fin density — higher FPI (fins per inch) increases surface area but raises pressure drop; optimal: 14–22 FPI for 1U/2U servers
Fin height — diminishing returns above ~50 mm due to thermal boundary layer growth; effectiveness η drops below 60%

R_spreading: For 60×60 mm die on 120×120 mm base: ~0.02–0.05 °C/W in copper, ~0.05–0.12 °C/W in aluminium
R_conv: Forced air at 3 m/s: 0.08–0.15 °C/W for a 2U server heatsink

Heat Pipe Integration

Sintered heat pipes — Q_max = 30–80 W per 6 mm pipe; effective k > 10,000 W/m·K along length
U-shape / L-shape — transport heat from baseplate to remote fin stacks; enables offset designs for RAM clearance
Gravity-dependent: performance degrades 10–30% in adverse orientation (evaporator above condenser)

Air cooling limit: practical maximum ~350–400 W for a 2U server heatsink at 35 °C inlet, 80 dBA acoustic budget. Beyond this, liquid cooling becomes necessary.

1U Server

≤200 W

Active heatsink

2U Server

≤400 W

Heatpipe tower

4U / OAM

≤700 W

Vapour chamber

Vapour Chambers

A vapour chamber is a planar heat pipe: a sealed copper enclosure with an internal wick structure and working fluid (water). It provides near-isothermal heat spreading across the entire baseplate area.

Operating Principle

1. Evaporation at hotspot

↓

2. Vapour transport (near-sonic)

↓

3. Condensation at cooler walls

↓

4. Wick return (capillary action)

Effective k: 20,000–50,000 W/m·K (vs 400 for solid copper)
Thickness: 2.5–4.0 mm typical; ultra-thin: 0.4 mm for mobile
Q_max: 200–500 W for 80×80 mm chamber; limited by wick capillary limit and boiling limit

GPU / Accelerator Applications

AMD MI300X — custom vapour chamber spans entire 5,332 mm² OAM module; R_spreading < 0.01 °C/W
NVIDIA H100 SXM — vapour chamber baseplate with extruded fin stack; handles 700 W TDP
Wick types — sintered copper powder (most common), mesh, grooved, or hybrid multi-layer for higher capillary pressure
Manufacturing — diffusion bonding or brazing; vacuum backfill with degassed DI water; leak rate < 10⁻⁸ atm·cc/s

Spreading Solution	R_spread (°C/W)	Weight (g)
Solid copper (6 mm)	0.08	580
Copper + heat pipes	0.04	320
Vapour chamber (3 mm)	0.015	180

Fan & Airflow Design

CFD-Optimised Airflow

Airflow requirement — ~100–200 CFM per GPU at 700 W; total server (8-GPU): 800–1600 CFM
Pressure drop — dense fin arrays create 0.5–2.0 inches H₂O static pressure; requires high-static-pressure fans (counter-rotating or multi-stage)
Push-pull — dual fan walls increase effective static pressure by ~60%; standard in DGX-style 8-GPU servers
CFD validation — ANSYS Icepak / 6SigmaET simulations validated with IR thermography and thermocouple data; typical accuracy ±3 °C

Fan power: 200–600 W per server (5–10% of total system power); proportional to RPM³
Acoustic: 70–85 dBA at 1 m for datacenter; ≤40 dBA for workstation

Server Rack Airflow Management

Front-to-back — standard airflow direction; cold air from cold aisle, exhaust to hot aisle
Air recirculation — primary failure mode; hot exhaust re-entering intake raises T_inlet by 5–15 °C; containment curtains or doors eliminate this
Blanking panels — seal unused U-spaces; missing panels can raise intake temp by 8 °C
Dust filtration — MERV-8 minimum for datacenter; high-altitude sites (Mexico City, Denver) need MERV-11+ due to particulate density

Air cooling economics: fan power at full speed (85 dBA) for an 8×H100 DGX system consumes ~500 W — 7% overhead. Liquid cooling reduces this to ~50 W (pumps), saving 450 W per node × 1000s of nodes.

Section III

Liquid Cooling

Cold plates · Direct liquid cooling · Immersion · Coolant distribution

Cold Plate Liquid Cooling

Direct-to-Chip Cold Plates

Copper cold plate — brazed or skived-fin internal channels; turbulent flow at Re > 4000 provides h = 5,000–15,000 W/m²·K
Microchannel designs — channel width 50–500 μm; R_th < 0.02 °C/W for 700 W class; limited by pressure drop (0.5–3 bar)
Jet impingement — coolant jets directly on cold plate surface; h up to 25,000 W/m²·K; used in custom HPC systems

Flow rate: 0.5–2.0 L/min per GPU; ΔT_water = P/(ṁ·c_p) ≈ 700/(0.017×4186) ≈ 10 °C at 1 L/min
Pressure drop: 0.3–1.5 bar per cold plate; total loop: 2–4 bar
R_total: 0.03–0.06 °C/W (cold plate only, excluding TIM)

Coolant Selection

Coolant	k (W/m·K)	c_p (J/kg·K)	Notes
Water	0.60	4186	Best thermal; corrosion risk
Water-glycol 30%	0.48	3600	Freeze protection to −15 °C
PAO (dielectric)	0.14	2100	Safe for electronics; 3× worse
Novec 7100	0.07	1180	Two-phase capable; expensive

Leak mitigation: non-drip quick-disconnect fittings (Staubli, CPC); leak detection sensors with auto-shutoff; redundant drain pans beneath every server.

Direct Liquid Cooling (DLC)

DLC delivers coolant directly to the chip package, bypassing heatsinks and airflow entirely. TSMC's direct-to-silicon approach achieves 0.055 °C/W at 2.6 kW — 3× better than the best air-cooled solutions.

CDU Architecture

Chip Cold Plate (40–50 °C)

↓ Secondary Loop (treated water)

In-Row CDU (heat exchanger)

↓ Primary Loop (facility water)

Cooling Tower / Dry Cooler

Secondary loop: Treated water, 35–45 °C supply, 2–4 bar, flow ~50–200 L/min per rack
CDU capacity: CoolIT, Vertiv, ZutaCore: 40–100 kW per CDU

Rear-Door Heat Exchangers (RDHx)

Passive RDHx — water coil on rack rear door; cools exhaust air by 15–25 °C; handles 30–50 kW/rack without facility CRAC changes
Active RDHx — integrated fans + coil; up to 60 kW/rack; Schneider NetShelter, Vertiv Liebert
Neutral air — exhaust exits at room temperature; eliminates hot aisle containment requirement

TSMC ECTC 2024: Si-integrated micro-cooler (IMC-Si) demonstrated 2.6 kW heat load at 4.8 W/mm² density with ΔT ~63 °C; ECTC 2025 paper integrated IMC-Si into production CoWoS-R packaging — the key enabler for 2 kW+ Rubin-class GPUs.

Immersion Cooling

Single-Phase Immersion

Principle — servers submerged in dielectric fluid (mineral oil, synthetic ester, or engineered fluids); natural or forced convection removes heat
h coefficient — 200–1500 W/m²·K (natural convection in dielectric); modest but uniform
Vendors — GRC (ElectroSafe), LiquidCool Solutions, Submer, Asperitas
Capacity — 100–200 kW per tank; suitable for racks up to 100 kW

Two-Phase Immersion

Boiling heat transfer — fluid boils on chip surface; h = 5,000–20,000 W/m²·K; latent heat absorption is extremely efficient
Fluid — historically 3M Novec 7100/649 (T_boil = 49–61 °C); 3M ceased PFAS production in 2025. Replacements: Chemours Opteon 2P50, Engineered Fluids ElectroCool, Solvay Galden. PFAS regulatory pressure and GWP drive the transition.
Condenser — vapour rises, condenses on water-cooled coils above tank; drips back (passive, no pumps for dielectric)

Deployment & PUE Impact

Cooling Method	PUE	kW/rack	Water Use
Traditional air (CRAC)	1.5–2.0	10–25	High (evap towers)
Hot aisle containment	1.2–1.4	20–40	Moderate
Direct liquid (DLC)	1.05–1.15	40–100+	Low (closed loop)
Single-phase immersion	1.02–1.10	100–200	Very low
Two-phase immersion	1.01–1.06	200+	Near zero

PUE savings at scale: a 100 MW AI data center at PUE 1.05 (immersion) vs 1.4 (air) saves 35 MW of cooling power — $25M+/year in electricity at $0.08/kWh.

"Two-phase immersion is the endgame for AI cooling, but fluid cost ($50–200/L) and serviceability remain barriers."
— Uptime Institute, 2025

Section IV

On-Die Thermal Management

Hotspot detection · Workload migration · Thermal throttling · 3D stacking challenges

Hotspot Mitigation

Non-Uniform Power Maps

Power map variance — tensor cores can hit 2–3 W/mm² locally while SRAM regions run at 0.3 W/mm²; hotspot-to-average ratio of 5–8× is common
On-die thermal sensors — 16–64 distributed diode sensors per die; sampled at 1–10 kHz; ring oscillator sensors provide finer spatial granularity
Thermal sensor accuracy — ±1–3 °C after one-time calibration at wafer sort; digital readout via ADC with 10–12 bit resolution

Sensor count: H100: 32 thermal diodes; MI300X: 48 per XCD; Gaudi 3: ~24
Response time: Silicon thermal time constant: 1–10 ms; sensor polling must be ≤ 1 ms for effective control

Mitigation Strategies

Floorplan optimisation — interleave high-power (compute) and low-power (SRAM, I/O) blocks; avoid clustering tensor cores
Dynamic workload migration — OS/firmware redistributes threads away from hot regions; effective for multi-core CPUs, less so for fixed-function accelerators
Power gating rotation — temporarily disable hotspot SM/CU clusters and redistribute work to cooler units; 5–10% throughput cost
HBM/logic thermal coupling — in 2.5D packages (CoWoS), HBM stacks (T_j,max = 95 °C for HBM3e) are heated by adjacent logic die; thermal guard rings and interposer-level heat spreading required

HBM thermal limit: HBM3e junction limit is 95 °C (JEDEC), only 10 °C above nominal — tighter than the logic die. HBM is often the first component to trigger throttling on 2.5D AI accelerators.

Thermal Throttling

Hardware Throttling Mechanisms

PROCHOT# — bidirectional signal; asserted when T_j exceeds thermal control threshold (e.g., 97 °C); triggers immediate frequency reduction
Thermal trip — hard shutdown at T_j = 105–115 °C; non-maskable; prevents silicon damage; hysteresis of 10–20 °C before restart
DVFS throttling — reduce V_core and frequency together; P ∝ V²f, so 10% frequency reduction yields ~27% power reduction
Clock gating — disable clocks to idle functional units; fine-grained (per-SM) in modern GPUs; response time < 1 μs

Firmware Thermal Control Loop

Thermal Sensors (diodes, ring osc)

↓ ADC @ 1–10 kHz

Thermal Controller (PID loop in FW)

↓ Target: T_j ≤ T_throttle

Actuators: DVFS, power limit, fan PWM

Control period: 1–10 ms for GPU thermal controller; 100 ms for BMC fan control
Hysteresis: Typically 5–10 °C between throttle-on and throttle-off to prevent oscillation
NVIDIA GPU Boost: Continuously adjusts clock within thermal/power envelope; ~100 MHz steps every 10 ms

3D Stacking Thermal Challenges

Inter-Die Thermal Resistance

Die-to-die bonding — hybrid bonding (Cu-Cu): R_th = 0.5–2.0 °C·mm²/W; micro-bump (solder): R_th = 5–15 °C·mm²/W; underfill thermal conductivity: 0.3–0.7 W/m·K
TSV thermal paths — copper TSVs (k = 400 W/m·K) act as thermal vias; at 10 μm pitch and 30% area coverage, effective through-silicon conductivity doubles
Bottom die trapped heat — in face-to-face bonding, bottom die has no direct path to heatsink; heat must flow through top die or through substrate (R_th,sub > 5× R_th,top)

HBM3e stack: 12-high die stack; R_th from base to top DRAM ≈ 4–8 °C/W; limits per-stack power to ~20 W
SoIC thermal: TSMC SoIC bond pitch < 10 μm; R_th improved 3–5× over micro-bump

Solutions for 3D Thermal

Backside power delivery (BSPDN) — frees frontside for cooling; Intel PowerVia (Intel 18A, 2025), TSMC Super Power Rail (A16, H2 2026); reduces R_jc by thinning the thermal path
Thermal TSVs — dedicated copper pillars (40–100 μm diameter) placed in non-functional areas; 20–40% R_th reduction
Microfluidic inter-die cooling — research: IMEC/Georgia Tech demonstrated microchannels between bonded dies; coolant flows between die layers; R_th < 0.5 °C/W at 250 W/cm²
Foveros thermal limit — Intel Foveros currently limited to ~1 W/mm² combined stack power; active cooling between layers needed for >3D stacks

The 3D thermal wall: without inter-die cooling, 3D stacks are limited to ~200 W total. Microfluidic and backside cooling are critical enablers for true 3D compute scaling.

Section V

System & Data Center Thermal

Rack-level cooling · Hot/cold aisle · AI supercomputer cooling · ASHRAE guidelines

Data Center Thermal Architecture

Rack-Level Power Density

Era	Rack Power	Cooling Method
2015 — General compute	5–10 kW	Raised floor air
2018 — GPU training	20–30 kW	In-row CRAC + containment
2023 — H100 era	40–70 kW	DLC + RDHx
2025 — B200 / MI300X	80–120 kW	Full DLC or immersion
2026+ — Rubin / next-gen	120–200 kW	Advanced liquid, microfluidic

ASHRAE A1: 15–32 °C dry bulb inlet; recommended for most datacenter equipment
ASHRAE W32: Liquid cooling class: ≤32 °C supply water; enables free cooling in most climates
Free cooling hours: W32 in N. Europe: ~8,500 hrs/yr; in Phoenix: ~4,000 hrs/yr

Hot/Cold Aisle Containment

Cold aisle containment — enclose cold aisle with doors + roof; prevents mixing; reduces CRAC energy by 20–30%; supply air 18–24 °C
Hot aisle containment — enclose hot aisle; exhaust directly to return plenum; allows higher supply temps (27 °C+) for more free cooling hours
Chimney cabinets — vertical exhaust ducts on rack top; direct hot air to ceiling plenum; popular in retrofit scenarios

Liquid-to-Liquid vs Liquid-to-Air

Liquid-to-air — dry coolers on rooftop; no water consumption; limited by ambient wet-bulb temperature; viable to ~40 kW/rack
Liquid-to-liquid — cooling towers or evaporative condensers; higher efficiency; WUE of 0.5–1.5 L/kWh; required for >60 kW/rack in hot climates

AI Supercomputer Cooling

NVIDIA DGX SuperPOD

DGX B200 — 8×B200 GPUs × 1000 W = 8 kW GPU + ~4 kW system = ~12 kW per node
SuperPOD — 32–64 DGX nodes; 384–768 kW total; requires DLC (CoolIT or Vertiv manifolds)
NVLink domain — 72 GPUs connected via NVLink Switch; cable tray thermal management adds 2–5 kW

Google TPU Pod

TPU v5p pod — 8,960 chips; estimated 2–3 MW total; liquid-cooled with proprietary cold plates
TPU v6 (Trillium) — 4× performance/watt improvement claimed; still liquid-cooled; pod scale increasing

Meta Grand Teton

Open Rack v3 — 48V power shelf; designed for 100 kW/rack; OCP-standard liquid cooling manifolds
Grand Teton platform — 8-GPU training platform; hybrid air+liquid; cold plate on GPUs, air for ancillary components

Microsoft Maia 100

Custom ASIC — TSMC 5 nm, ~820 mm²; TDP ~500 W; designed with liquid cooling as primary
Sidekick liquid cooling — proprietary cold plate with integrated manifold; designed for >100 kW/rack density
Co-design — chip and cooling system designed simultaneously; thermal constraints fed back to floorplan team from day one

Trend: every major AI hyperscaler now designs custom cooling alongside custom silicon. Thermal co-design is no longer optional.

Case Studies

NVIDIA H100 / B200

H100 SXM: 700 W, vapour chamber heatsink, air-cooled baseline; DLC option with CoolIT cold plate (R_th = 0.04 °C/W)
B200: 1000 W, DLC mandatory; dual-die (2×Blackwell) on CoWoS-L; custom liquid manifold per baseboard
Grace-Blackwell NVL72: 72 GPUs in liquid-cooled rack; ~120 kW/rack

AMD MI300X

750 W TDP; 12 chiplets (8 XCD + 4 IOD) on CoWoS-equivalent; massive 5,332 mm² package
Custom vapour chamber spans full OAM module footprint; R_spreading < 0.01 °C/W
HBM3 stacks at package edges reduce thermal coupling; T_HBM managed to ≤89 °C under load

Intel Ponte Vecchio

600 W TDP; 47 tiles on Foveros + EMIB; base tile and compute tiles in 3D stack
Liquid cooled from launch (Aurora supercomputer); cold plate with microchannel inserts; R_th,total ≈ 0.055 °C/W
Thermal challenge: non-uniform power across 47 tiles; FEM-guided tile placement optimisation

TSMC Direct-to-Silicon

Microchannels etched into silicon backside (50 μm wide, 200 μm deep); coolant flows directly over active die
Demonstrated 2.6 kW with R_th = 0.055 °C/W; ΔT_j = 143 °C → T_j ≤ 180 °C (test) / designed for T_j ≤ 90 °C at 1 kW
Roadmap: production-ready by 2026–2027; enables >1500 W accelerators on A16 / Intel 18A (BSPDN); N2/N2P retain frontside power

References & Further Reading

Books & Standards

Incropera, DeWitt et al. — Fundamentals of Heat and Mass Transfer, 8th Ed., Wiley, 2017
Bar-Cohen, A. — Encyclopedia of Thermal Packaging, World Scientific, 2013
JEDEC JESD51 — thermal measurement standards (JESD51-1 through JESD51-14); defines R_jc, R_ja methodologies
ASHRAE TC 9.9 — Thermal Guidelines for Data Processing Environments, 5th Edition (2021); superseded in 2024 by the continuously-updated ASHRAE Datacom Encyclopedia
Mahajan, R. et al. —"Embedded Multi-Die Interconnect Bridge," IEEE ECTC 2016

Papers

TSMC —"Direct Liquid Cooling of High-Performance Chips," IEEE ECTC 2024
Wei, J. —"Challenges in cooling design of CPU packages," Heat Transfer Engineering, 29(2), 2008
IMEC —"Microfluidic cooling for 3D-stacked ICs," IEEE 3DIC 2023

Industry Resources

NVIDIA — DGX B200 System Design Guide; thermal architecture white papers
CoolIT Systems — Direct Liquid Cooling reference architectures for OCP/OAM
Vertiv — Liebert CDU sizing guides; PUE analysis tools
Open Compute Project (OCP) — OAM v2 specification; Advanced Cooling Solutions workgroup
GRC / LiquidCool — Immersion cooling deployment guides and TCO calculators

Next: Presentation 13 — next topic in the Modern SoC Design series

Presentation built with Reveal.js 4.6 · Saira Semi Condensed + Archivo + Share Tech Mono
Educational use. Data from public specifications and published papers.

Thermal Management inML Accelerator SoCs