MODERN SOC DESIGN · PRESENTATION 01

SoC Packaging

From Wire Bonds to 3D Chiplets & Beyond

Wire bond · Flip-chip · Fan-out · 2.5D interposers · 3D stacking · Chiplets · CoWoS · EMIB · Foveros · UCIe

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Why Packaging Matters

Performance — interconnect latency & bandwidth between die and memory now dominate system bottlenecks
Power — off-chip I/O burns 5–10× more energy per bit than on-die interconnect
Cost — yield drops exponentially with monolithic die area; chiplets restore economics
Integration — heterogeneous process nodes (logic, analog, I/O, memory) on a single package

"Packaging, not chip manufacturing, is now the primary supply constraint for AI accelerators."
— Industry consensus, 2025

Advanced packaging market: ~$45B in 2024 → projected ~$80B by 2030 (CAGR ≈ 9.4%)

Packaging Evolution

DIP → QFP → BGA → Flip-Chip → Fan-Out → 2.5D → 3D

Traditional Package Types

Era	Package	I/O Count	Key Feature	Limitation
1970s	DIP Through-hole	8–64	Simple, hand-solderable	Low density, high inductance
1980s	QFP SMD	44–304	Peripheral leads, fine pitch	Fragile leads, coplanarity
1990s	BGA Area-array	100–2000+	Solder balls underneath	Inspection difficulty
2000s	Flip-Chip BGA Bumped	1000–5000+	Die face-down; short interconnects	Underfill, CTE mismatch
2010s+	Fan-Out WLP eWLB	500–3000+	RDL routing beyond die edge	Die shift, warpage

Wire Bond → Flip-Chip

Wire Bond

Mold Compound

Au / Cu wires (peripheral pads → lead frame)

Die (face-up)

Die Attach (epoxy / solder)

Lead Frame / Substrate

Peripheral-only I/O → limited pin count
Long wire inductance (2–5 nH)
Still dominant for low-cost MCUs, sensors

Flip-Chip (C4 / μ-bump)

Lid / Heat Spreader

Die (face-down)

Solder bumps (area-array, 100–150 μm pitch)

Underfill (CTE stress relief)

Organic Substrate (multi-layer)

BGA solder balls → PCB

Area-array → 5000+ I/O
Short interconnects (~50 pH inductance)
Better thermal path (die → heat sink)

Fan-Out Wafer-Level Packaging

Redistribution Layers (RDL) — Cu/PI, 2–5 μm L/S

Known Good Die (KGD)

Mold Compound (epoxy reconstitution)

Solder Balls (fan-out area > die area)

The key innovation: the redistribution layer (RDL) routes signals from the die's fine-pitch pads to a larger fan-out area, enabling more I/Os without increasing die size.

TSMC InFO Variants

InFO-WLP — single die, mobile SoCs (Apple A-series since A10)
InFO-PoP — Package-on-Package; DRAM stacked above logic
InFO-L — large-scale fan-out with local silicon interconnect (LSI) bridges
InFO-M — multi-die fan-out for networking ASICs

Fan-out eliminated the package substrate for mobile SoCs, reducing Z-height by ~0.3 mm and improving power integrity.

2.5D Integration

Silicon interposers · RDL interposers · Embedded bridges

2.5D Architecture Concept

Multiple die placed side-by-side on a shared interposer, connected via fine-pitch interconnects

Logic SoC

HBM

μ-bumps (30–55 μm pitch) · fine-pitch Cu pads

Silicon / RDL Interposer (TSVs + multi-layer Cu RDL)

C4 / micro-C4 bumps

Organic Package Substrate

BGA solder balls → PCB

Bandwidth

μ-bump pitch enables TB/s-class die-to-die and die-to-HBM links

Power

Short interconnect (~1 pJ/bit) vs off-package (~10 pJ/bit)

Heterogeneous

Each die on optimal process node — logic at N3, I/O at N5/N7

TSMC CoWoS Family

Variant	Interposer	Max Size	Key Application	Interconnect
CoWoS-S	Silicon + TSVs	3.3× reticle (~2700 mm²)	NVIDIA H100, AMD MI300	Sub-μm Cu RDL, eDTC
CoWoS-R	RDL organic (polymer)	> 3.3× reticle	Cost-sensitive HPC	Wider pitch, lower cost
CoWoS-L	RDL + LSI chip bridges	5.5–9.5× reticle	NVIDIA B100/B200/B300, AMD MI355X	LSI for fine-pitch D2D, RDL for coarse

CoWoS-L innovation: Local Silicon Interconnect (LSI) chips provide sub-μm die-to-die links where needed, while an organic RDL interposer handles power distribution and coarse routing over a much larger area — breaking the reticle size limit of pure silicon interposers.

Capacity ramp:

2024	35–40K wafers/month
2025	65–90K wafers/month
2026e	120–135K wafers/month

NVIDIA alone: ~63% of CoWoS demand

Intel EMIB — Embedded Multi-Die Interconnect Bridge

Chiplet A

Chiplet B

μ-bumps at bridge region only

Organic Substrate EMIB Bridge

BGA → PCB

Small silicon bridge embedded inside the organic substrate cavity — only where die-to-die links are needed.

EMIB vs CoWoS

Aspect	EMIB	CoWoS
Interposer	None (local bridge)	Full interposer
TSVs	Not required	Required (silicon)
Scalability	Modular bridges	Reticle-limited
Cost	Lower per bridge	Higher (large Si)
Best for	ASICs, networking	GPU + HBM

Mass production since 2017 (Stratix 10 MX FPGA); used in Ponte Vecchio, Granite Rapids.

Competitive Landscape — 2.5D

Company	Technology	Approach	Status
TSMC	CoWoS-S/-R/-L	Silicon + RDL + LSI hybrid interposers	HVM Market leader
Intel	EMIB / EMIB 3.5D	Embedded silicon bridges in substrate	HVM Since 2017
Samsung	I-Cube / H-Cube	Silicon interposer (I-Cube); hybrid 2.5D+3D	Ramp
ASE	FOCoS / VIPack	Fan-out + silicon bridge + TSV	Ramp
Amkor	S-Connect / 2.5D Si	Silicon interposer, TSMC-partnered	Expanding AZ campus (up to $7B, 2028+)

OSATs (ASE, Amkor, SPIL) are building CoWoS-like capacity as second-source options for fabless customers.

3D Integration

Die-on-die stacking · TSVs · Hybrid bonding · SoIC · Foveros

3D Die Stacking — Vertical Integration

Compute Chiplet (N3)

Hybrid Bond (Cu-Cu, <1 μm pitch)

I/O Die (N5/N6)

TSVs through I/O die

2.5D Interposer

Package Substrate

AMD MI300X: XCDs (N5) 3D-stacked on IODs (N6), then placed on 2.5D Si interposer with HBM3 — a "3.5D" architecture.

Bonding Technologies

Method	Pitch	Density
μ-bump (solder)	30–55 μm	~400/mm²
Cu pillar	20–40 μm	~1000/mm²
Hybrid bond	0.5–9 μm	10K–1M/mm²

Hybrid bonding (Cu-Cu direct bond) enables 100–1000× the interconnect density of μ-bumps, unlocking true 3D logic stacking with massive inter-die bandwidth.

TSMC SoIC & Intel Foveros

TSMC SoIC

SoIC-X — Chip-on-Wafer, face-to-face hybrid bonding (finest pitch, highest density)
SoIC-P — Chip-on-Wafer, face-to-back, TSV-based; allows >2 die stacking tiers
Combined with CoWoS in CoWoS+SoIC for full 3.5D system integration
Used in AMD MI300 series (logic-on-logic stacking)

$3.5B+ investment in SoIC capacity across multiple Taiwan sites

Intel Foveros

Foveros — original die-on-die with μ-bumps (Lakefield, 2019)
Foveros-S — silicon interposer variant
Foveros-R — RDL fan-out interposer
Foveros-B — silicon bridge variant
Foveros Direct — hybrid bond (<10 μm pitch, Cu-Cu)
Combined with EMIB → "3.5D" integration (Ponte Vecchio)

$3.5B New Mexico facility dedicated to Foveros

Chiplet Architecture & Standards

Disaggregation · UCIe · Die-to-die protocols

The Chiplet Rationale

Monolithic Die Problems

Yield: At N3, a 600 mm² die may have <30% yield; two 300 mm² chiplets can exceed 70% each
Cost: Advanced node wafers cost $20–30K; smaller die = more per wafer
Flexibility: Can't mix process nodes on one die (analog ≠ logic ≠ I/O)
Reticle limit: Max ~858 mm² per lithography exposure

Chiplet Advantages

Yield recovery: Smaller die → quadratic yield improvement
Mix & match: Compute at N3, I/O at N5, SerDes at N7 — each optimised
IP reuse: Same chiplet across product families (AMD CCD → EPYC, Ryzen, Threadripper)
Time-to-market: Parallel development of independent die

AMD's proof point: A single Zen CCD chiplet design is reused across consumer (Ryzen), workstation (Threadripper), and server (EPYC) product lines — varying only the I/O die and chiplet count per package.

UCIe — Universal Chiplet Interconnect Express

The "USB for chiplets" — an open standard for die-to-die communication

Spec	UCIe 1.0	UCIe 2.0	UCIe 3.0
Data Rate	4–32 GT/s	32 GT/s	64 GT/s
Reach	Standard + Advanced	Extended	+ 100 mm sideband
Protocols	PCIe, CXL	+ streaming	+ priority, throttle
Released	2022	2024	Aug 2025

Protocol Stack

Application (PCIe / CXL / Custom)

Protocol Layer (flit format)

Die-to-Die Adapter (retry, CRC)

Physical Layer (SerDes / forwarded clock)

Bump/pad interface (standard or advanced)

Consortium members: AMD, Arm, ASE, Google, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung, TSMC, and 100+ others

Thermal & Power Challenges

PDN integrity · TDP scaling · Advanced cooling · BSPDN

Power Delivery in Advanced Packages

As AI accelerators cross the 1000W TDP line (NVIDIA B200) and push toward 1400–2300 W (B300 / Rubin VR200), power delivery through the package becomes critical.

Challenges

IR drop across interposer RDL and substrate
Simultaneous switching noise (SSN) with TB/s I/O
Decoupling capacitance density requirements
VRM-to-die impedance at >100A current

Solutions

eDTC — embedded Deep Trench Capacitors in interposer (CoWoS-L); high-density decoupling directly under die
PIVR — Package-Integrated Voltage Regulators (Marvell); VRM inside the package
BSPDN — Backside Power Delivery Network; separate power and signal to different die faces
IVR on die — Integrated voltage regulators for per-domain DVFS

TSMC BSPDN arrives in A16 ("Super Power Rail"), H2 2026 — power rails on wafer backside, freeing frontside for signal routing density. N2/N2P use conventional frontside power delivery.

Thermal Management

The Heat Problem

3D stacking creates buried hot spots with no direct path to heatsink
CTE mismatch (Si ≈ 2.6 ppm/°C vs organic ≈ 17 ppm/°C) causes warpage and solder fatigue
HBM stacks are thermally constrained (~1.2W per die layer, cumulative)
Data center racks exceed 100 kW with advanced GPU nodes

Cooling Technologies

Lid engineering — IHS with vapor chamber, TIM1/TIM2 optimization
Direct liquid cooling — cold plates on package; TSMC demonstrated 0.055 °C/W at 2.6 kW+ TDP on CoWoS
Microfluidic channels — etched into silicon interposer backside
SiC interposers — silicon carbide offers 3× the thermal conductivity of Si (exploring stage)

TSMC demonstrated direct-to-silicon liquid cooling on CoWoS at IEEE ECTC 2025, achieving 0.055 °C/W thermal resistance at 2.6 kW TDP on a 3,300 mm² interposer.

Case Studies

NVIDIA Blackwell · AMD MI300X · Apple M-series · Intel Ponte Vecchio

NVIDIA Blackwell B200

Process	TSMC N4P
Package	CoWoS-L (5.5× reticle+)
Architecture	Dual compute chiplets
D2D Link	10 TB/s NV-HBI (custom)
Memory	8× HBM3E stacks
HBM BW	8 TB/s aggregate
TDP	1000W (SXM/HGX)
Transistors	208 billion

Packaging Innovations

Two GPU chiplets connected by 10 TB/s NV-HBI — appear as single coherent GPU to software
CoWoS-L enables a package far exceeding single-reticle limits
LSI bridges provide fine-pitch D2D between chiplets
eDTC on interposer for power integrity at >700W
NVIDIA reportedly secures ~70% of TSMC's CoWoS-L capacity

Blackwell demonstrates that advanced packaging is now the primary enabler of GPU scaling — die size no longer limited by lithography.

AMD MI300X — 3.5D Integration

XCDs	8× CDNA 3 compute (TSMC N5)
IODs	4× I/O die (TSMC N6)
3D Bond	XCDs hybrid-bonded onto IODs (SoIC)
2.5D	Stacked die on CoWoS-S Si interposer
HBM	8× HBM3 stacks (192 GB)
TDP	750W
Transistors	153 billion

Architecture Stack

XCD

Hybrid Bond (SoIC)

I/O Die (IOD)

μ-bumps

Si Interposer (CoWoS-S)

Package Substrate

First production GPU to combine 3D stacking (logic-on-logic) with 2.5D interposer integration.

More Packaging Case Studies

Apple M2 Ultra

Two M2 Max dies connected via UltraFusion — a custom silicon interposer bridge providing 2.5 TB/s die-to-die bandwidth. Uses TSMC InFO + silicon bridge.

Appears as unified SoC to macOS

Intel Ponte Vecchio

47 active tiles, 5 process nodes, 100B+ transistors. Combines Foveros (3D stacking), EMIB (2.5D bridges), and standard packaging in one product.

Most complex IC package ever produced (2023)

AMD EPYC (Zen 5)

Up to 16 CCDs (Zen 5 compute) connected to a central IOD via Infinity Fabric. Each CCD is a reusable chiplet — same die as Ryzen consumer parts.

Chiplet economics: 1 CCD design → 4+ product families

Future Directions

Panel-level packaging · Photonics · System-on-Wafer · SiC substrates

What's Next?

FoPLP

Fan-Out Panel-Level Packaging — move from 300 mm wafers to 600×600 mm panels. Dramatically lower cost per unit area for large packages.

Co-Packaged Optics (CPO)

Photonic transceivers integrated into the package. Eliminates electrical I/O bottlenecks for data center interconnect at 100+ Tbps per package.

System-on-Wafer (SoW)

TSMC's SoW-X architecture — entire wafer-scale integration for extreme AI/HPC. Complements Cerebras WSE approach at foundry level.

SiC Interposers

Silicon carbide as interposer material — 3× thermal conductivity of Si, better mechanical robustness. TSMC actively exploring for next-gen CoWoS.

Glass Substrates

Intel investing in glass core substrates — superior flatness, thermal stability, and ultra-fine through-glass vias (TGV) vs. organic substrates.

CoPoS

Chip on Panel on Substrate — TSMC's ultra-large-area approach complementing CoWoS for future AI/HPC packages beyond wafer-scale limits.

Packaging Decision Framework

How to choose the right packaging approach for your SoC

Requirement	Recommended Packaging	Example
Low cost, moderate I/O	Wire bond / QFP / standard BGA	IoT MCUs, sensors
High I/O, single die	Flip-chip BGA	Application processors, FPGAs
Thin profile, mobile	Fan-out WLP (InFO)	Apple A-series, Qualcomm Snapdragon
GPU + HBM (high BW)	2.5D CoWoS-S/-L	NVIDIA H100/B200, AMD MI300
Modular chiplets, ASIC	EMIB or fan-out bridge	Intel Ponte Vecchio, networking ASICs
Maximum integration	3D stacking (SoIC/Foveros) + 2.5D	AMD MI300X (3.5D hybrid)
Ultra-scale AI	SoW / FoPLP / CoPoS	Next-gen data center accelerators

Key Metrics Comparison

Metric	Wire Bond	Flip-Chip	2.5D CoWoS	3D Hybrid Bond
I/O Density	~20/mm	~25/mm²	~400/mm²	10K–1M/mm²
Bump Pitch	50–60 μm pad	100–150 μm	30–55 μm	0.5–9 μm
D2D BW	—	—	TB/s class	Multi-TB/s
Energy / bit	~5 pJ	~2 pJ	~0.5 pJ	~0.05 pJ
Rel. Cost	1×	2–3×	5–10×	10–20×
Heterogeneous	No	Limited	Yes	Yes (3D)

Summary & Key Takeaways

Packaging is the new scaling vector — as Moore's Law slows, advanced packaging enables continued system-level performance gains through heterogeneous integration
2.5D is mainstream for HPC/AI — CoWoS and EMIB are in high-volume manufacturing, with demand exceeding supply through 2027
3D stacking is production-ready — hybrid bonding enables logic-on-logic (MI300X) and will expand to logic-on-memory
Chiplets + UCIe enable modular SoC design — disaggregation improves yield, enables IP reuse, and allows mixing of process nodes
Thermal & power delivery are the binding constraints — liquid cooling, BSPDN, eDTC, and SiC substrates are all being deployed to keep pace with 700W+ TDPs
The supply chain matters — CoWoS capacity is the bottleneck for AI chip production; packaging facilities are receiving billions in investment worldwide

References & Further Reading

TSMC 3DFabric — CoWoS, InFO, SoIC technology documentation
Intel Packaging — EMIB, Foveros, glass substrate technology briefs
UCIe Consortium — Universal Chiplet Interconnect Express specifications (1.0, 2.0, 3.0)
Yole Group — "State of Advanced Packaging 2024" market report
IEEE ECTC 2025 — TSMC direct-to-silicon liquid cooling demonstration
JEDEC — HBM3/HBM3E (JESD238), HBM4 (JESD270-4, Apr 2025)
AMD — MI300X architecture white paper; EPYC chiplet design methodology
NVIDIA — Blackwell architecture technical overview
Lau, J.H. — Semiconductor Advanced Packaging, Springer, 2021
Vivet, P. et al. — "Chiplet-based architecture for edge AI computing," IEEE JSSC, 2023

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