A power delivery network is not a ladder of components but an ecology, and its largest feature belongs to nobody: the antiresonance between the die's own capacitance and the inductance of the package that connects it to everything else.
Deck 11 treated the network as a ladder of parallel branches, which is right as far as it goes and stops being right above the first cavity resonance. The better picture, and the one Smith and Bogatin insist on, is an ecology: a sequence of elements each of which dominates a band, with the interesting behaviour living in the handovers between them rather than in any one element.
Read down the table and one thing stands out. Every handover is a place where a capacitive branch meets an inductive one, and every such meeting is a parallel resonance. The profile of a real network is therefore a series of peaks by construction, and the design problem is choosing where they sit and how tall they are rather than eliminating them.
One of them is different from the rest. The on-die capacitance and the package inductance are on opposite sides of a boundary that the board cannot reach across, so the peak between them is fixed by the die and the package alone. It is usually the tallest feature in the profile and it is the subject of slides 04 to 06.
Between two points in a wide plane cavity, the inductance is not proportional to the area of the planes. It depends on the logarithm of the separation divided by the contact radius, scaled by the plate spacing:
$$L_{\text{spread}} \approx \frac{\mu_0 h}{2\pi}\ln\!\left(\frac{d}{r}\right).$$
Two consequences follow, and both are counter-intuitive enough to be worth stating explicitly.
Halving the dielectric between power and ground halves the inductance directly. That is why the two planes are placed on adjacent layers and as close together as the stackup allows — not for the capacitance, which is a secondary benefit, but for the inductance.
Moving a capacitor from twenty-five millimetres to one buys a factor of two or three, not a factor of twenty-five. Getting a capacitor close is worth doing and is not the dramatic lever it is often described as; shortening its mounting loop, from deck 11, is the bigger one.
The deeper consequence is on the next slide. If the inductance between two points depends on where those points are, then the impedance of the network is a property of a pair of locations, and "the PDN impedance" is not a single number.
A plane pair is a resonant cavity, and each of its modes contributes in proportion to the product of the mode shape evaluated at the two contact points. A probe sitting on the node of a mode does not see that mode at all; one sitting on an antinode sees it fully.
It means a power-plane impedance measurement is only meaningful with its probe locations recorded, and that a measurement taken at a convenient test point can differ substantially from what the load at the other end of the board experiences. Deck 13 is about making such a measurement honestly; this slide is about what it is a measurement of.
Seen from the die, the on-die decoupling capacitance sits in parallel with everything beyond the package — and everything beyond the package is behind the package's lead inductance. Those two resonate. Because the die capacitance is large and the package inductance small, the resonance lands in the tens to hundreds of megahertz, which is exactly where core logic switches.
The feature was named the Bandini Mountain by Steve Weir, after a fertiliser company whose works were a well-known landmark on the approach to Los Angeles. The joke is affectionate and the point is serious: it is usually the tallest thing in the profile, and it is not on the board.
The peak's height is set by how much resistance lies in the loop. Its characteristic impedance, $\sqrt{L/C}$ of the resonating pair, is the natural scale: with much less resistance than that the peak is tall and narrow, and with resistance of that order it is barely a peak at all.
Because the resonance is between two elements neither of which is on the board, the board's options are limited to damping. What genuinely moves it is silicon and packaging.
More on-die capacitance moves the peak down in frequency and lowers its characteristic impedance, which lowers the peak too — a double benefit, and the reason on-die decoupling capacitance is spent so freely despite costing area. Lower package inductance does the same, which is one of the arguments for flip-chip over wire bond and, further along, for putting regulation in the package.
More on-die capacitance. Lower package lead inductance. Deliberate resistance in the path, which is what controlled-resistance capacitors and the board's own copper loss provide.
Adding board capacitors. They are on the far side of the inductance that causes the resonance, so they cannot see it. This is the single most common wasted response to a measured Bandini peak.
On-package decoupling, which sits between the die and the package lead and therefore genuinely is inside the loop. It is expensive and it is why high-end packages carry capacitors at all.
Everything so far has been a frequency response. What an engineer sees on an oscilloscope is a voltage that dips when the load turns on, and the shape of that dip is the same information. The response below is obtained by transforming the network's own impedance against a current step, so nothing is put into it by hand.
The usual way to describe the first droop is that a sudden current demand drives $L\,di/dt$ across the package inductance. Smith's framing inverts that, and the inversion is worth adopting because it makes the design levers obvious.
Nothing off the die can respond in the first few tens of picoseconds, so the die draws the charge it needs out of its own capacitance. Then the resulting voltage difference across the package inductance is what pulls current in from the board. The droop is the cause of the current, not the consequence of it, and that ordering is the part worth adopting.
The depth of that first dip, though, is not the charge term alone. Two things happen during the edge: charge leaves the capacitance, which costs $Q/C_{\text{die}}$, and the same current crosses that capacitance's own series resistance, which costs $I R_{\text{die}}$ immediately and does not depend on how much capacitance there is. On the network modelled here the second is forty times the first, so a design that doubles on-die capacitance to fix a first-droop problem will find almost nothing changes. The metrics below separate the two rather than quoting their sum.
That the first droop is fixed on the die alone, so no board component can reduce it; that the second droop's depth depends on how long the package takes to respond, which is the package inductance; and that only the third is a board problem at all. The computation bears all three out, and adds a fourth: the deepest excursion of the whole response, divided by the step current, comes out within a few per cent of the peak of the impedance profile. The frequency and time domains are describing the same event.
Why adding board capacitance to a first-droop problem does nothing, and why the maximum operating frequency of a core is so often limited on the die rather than by anything a board designer can influence. It also explains why the rail is still far from its DC level a microsecond after the step: the bulk capacitance and the regulator work on a timescale the core does not care about.
| Quantity | Expression | Worth remembering |
|---|---|---|
| Spreading inductance | $\mu_0 h \ln(d/r)/2\pi$ | Proportional to plate spacing, logarithmic in distance |
| Cavity modes | $f_{mn}=\frac{c}{2\sqrt{\varepsilon_r}}\sqrt{(m/W)^2+(n/L)^2}$ | Set by the outline; impedance depends on probe position |
| Bandini frequency | $1/2\pi\sqrt{L_{\text{pkg}}C_{\text{die}}}$ | Tens to hundreds of MHz, where cores switch |
| Its characteristic impedance | $\sqrt{L_{\text{pkg}}/C_{\text{die}}}$ | The resistance needed to damp it |
| Board capacitors | — | Cannot reach it; they are behind the inductance that causes it |
| First droop, charge term | $Q/C_{\text{die}}$ | On-die capacitance alone; no board fix exists |
| First droop, resistive term | $I R_{\text{die}}$ | Usually the larger of the two, and capacitance does not touch it |
| Deepest droop | $I\,Z_{\text{peak}}$ | Which is why the peak of the impedance, not its average, is the specification |
| Eventual DC level | $I R_{\mathrm{dc}}$ | The regulator's problem, not the decoupling's — and microseconds away |
Deck 12 of eleven in Signal Integrity & High-Speed Digital Design. Every figure on this page is computed by si_models/deck12 and embedded as data; nothing is typed in by hand.
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