The only part of a channel that is manufactured by drilling, and the part that decides whether a backplane runs at twenty-eight gigabaud. A capacitor, an inductor and a resonator, depending entirely on which frequency you ask about.
Everything else in a channel is defined photographically, to tolerances of a few micrometres, in two dimensions. A via is a hole, drilled mechanically through a stack of laminate, plated, and then possibly drilled again from the other side to remove part of what was just plated. Its tolerances are an order of magnitude looser than anything else on the board, and it is the only feature that goes the third way — vertically, through every plane in the stackup.
That vertical passage is the problem. The barrel is a conductor threading through a series of copper planes, each of which has to have a clearance hole — an antipad — punched in it so that the barrel does not short to it. Between the barrel and the edge of each antipad there is capacitance. Along the barrel there is inductance, whose value depends on where the return current is allowed to flow. And if the signal enters at the top and leaves half way down, the remaining barrel hangs off the signal path as an open-circuited stub.
Pad and barrel facing the antipad edges. Dominant at low frequency, and the reason an unoptimised via pulls the impedance down.
A thin vertical conductor whose return has to find its way between planes. Dominant once the capacitance has been designed away.
An unused length of barrel is a quarter-wave stub. It does not degrade the channel; it removes a band of it entirely.
Handbooks give a formula for the inductance of a via: about $5.08\,h\,[\ln(4h/d) + 1]$ nanohenries with the dimensions in inches. It is a useful number and it is routinely misapplied, because it assumes the return current is far away. Inductance is a property of a loop, and a via does not have one until its return path is named.
The difference is not marginal. The same hundred-and-twenty-thousandth barrel is worth three nanohenries in isolation and a few tenths of a nanohenry with ground vias beside it, and the design decision that moves it between those values is where the ground vias go — which is deck 02's argument arriving in a different form.
Computed with the isolated-barrel expression and with Johnson's interplane expressions for one, two and four return vias. Quoting the first without the second is the most common way to get a via budget wrong, and it is pessimistic rather than optimistic — which is its own hazard, because it leads designers to avoid vias they could afford.
Three lumped descriptions of a via are in common use: a shunt capacitance alone, a series inductance alone, and a pi network with half the capacitance either side of the inductance. Which is adequate depends on frequency and on the via's own $\sqrt{L/C}$ relative to the channel impedance, and the ranges can be computed rather than guessed.
Validity is judged on the reflection coefficient in linear terms rather than in decibels, because at low frequency both a right and a wrong model predict a reflection too small to matter and a decibel comparison would call the simplification wrong for no useful reason.
Between two planes, a barrel surrounded by an antipad is a coaxial transmission line: an inner conductor, an outer conductor at the antipad edge, and dielectric between. It therefore has a characteristic impedance, $\left(60/\sqrt{\varepsilon_r} \right)\ln(D_{\text{anti}}/D_{\text{barrel}})$ per barrel, and if that impedance matches the channel the via stops being a discontinuity and becomes a short length of line.
This is the insight that made hundred-gigabit vias possible, and it points in a direction that surprises people: the answer is to make the clearance holes much larger than mechanical clearance requires. Opening the antipad raises the impedance towards the target and cuts the capacitance at the same time.
Every antipad is a hole in a reference plane. A dense array of them under a connector or a large package removes so much copper that the return paths of deck 02 are obstructed and the plane pair of deck 12 stops behaving like a plane pair. Via design is therefore not a local optimisation: the antipad that makes one transition transparent can be the antipad that ruins the power delivery.
A through-hole via is drilled through the whole board whether or not the signal needs to travel that far. A signal entering on layer two and leaving on layer four of a twenty-layer backplane leaves most of the barrel connected to the signal path at one end and connected to nothing at the other. That is an open-circuited stub, and an open-circuited stub a quarter of a wavelength long presents a short circuit at its base.
$$f_{\text{notch}} = \frac{c}{4\,\ell\,\sqrt{\varepsilon_r}}.$$
The distinction that matters is between attenuation and a notch. Attenuation removes amplitude and an equaliser can put it back, at the cost of amplifying noise along with it. A notch removes the information at those frequencies altogether, and nothing recovers it. This is the single most important reason a modern backplane is back-drilled.
Back-drilling removes the unused barrel with a larger drill from the far side. It cannot remove all of it: the drill must stop short of the signal layer by a manufacturing allowance, typically eight to twelve thousandths of an inch, or it will cut the connection it is supposed to preserve. A residual stub always remains, and the question is how much it costs.
Here is the result that changes how a via is designed. A barrel whose own impedance equals the channel impedance is not the best via. The launch — the pad, the clearance in the signal layer, the short run of trace reaching the barrel — is capacitive, and a capacitive discontinuity reflects with the opposite sign to nothing at all. A barrel slightly below the channel impedance reflects with the same sign as the launch capacitance in a way that partly cancels it.
Optimising the two together rather than separately is worth many decibels of return loss, and it comes with a trade-off the sweep makes visible: the cancellation is narrowband, so the antipad that minimises reflection at Nyquist is not the antipad that gives the widest usable bandwidth.
The lumped picture says a via gets monotonically worse as the board gets thicker, because the capacitance and the inductance both grow. The transmission-line picture says something more interesting: a mismatched section is invisible when it is a half wavelength long, and worst when it is a quarter. Thickness therefore does not degrade a via steadily — it moves the via along a periodic curve.
This is a real effect and a fragile one. Depending on a half-wave resonance to hide a mismatch ties the design to a particular thickness, a particular dielectric constant and a particular frequency, all of which move with the fabricator and the temperature. It is worth knowing about mainly so that a surprisingly good measurement on a thick board is not mistaken for a well-designed via.
Two signal vias passing through the same plane stack couple to each other, and the mechanism is not the one people assume. The direct field between the two barrels is the smaller part. The larger part is that they share a return via, and current from one signal flowing through that shared return develops a voltage that the other signal sees.
Johnson's result for the mutual inductance makes the structure of the problem explicit:
$$L_m = 5.08\,h\,\ln\!\left(\frac{s_1 s_3}{s_2 r}\right)\ \text{nH},$$
where $s_1$ and $s_3$ are the distances from the shared return via to the two signal vias and $s_2$ is the distance between the signal vias themselves. Note what the expression says: bringing the two signal vias further apart increases $s_2$ and reduces the coupling, but so does bringing the shared return via closer to both. Giving each signal via its own return via removes the mechanism entirely.
A connector is a via problem with mechanical constraints. Its pins pass through the board as press-fit through-holes, which cannot be back-drilled below the press-fit region, and its footprint perforates every plane it passes. The good high-speed connectors solve this by controlling the impedance of the pin field itself and by allocating a large fraction of the pins to ground, so that every signal pin has a return beside it.
Most of a connector's reflection comes not from the connector but from the transition between its footprint and the board's traces, where the impedance, the reference plane and the geometry all change within a few millimetres. It is the same optimisation as slide 07 with less freedom.
A connector with one ground pin per differential pair behaves quite differently from one with a ground pin on every side of every pair, and the difference appears as crosstalk rather than as insertion loss. Deck 06's integrated crosstalk noise is the figure that captures it.
A press-fit pin needs a certain barrel length to retain itself, which sets a floor on the stub that back-drilling can leave. On a thick backplane this floor, rather than the drill tolerance, is what limits the achievable residual.
A connector cannot be measured in isolation; it is always measured with two launches attached, and removing them is the de-embedding problem deck 16 is about. A connector datasheet is therefore a statement about a connector plus somebody else's fixture.
| Quantity | Expression | Worth remembering |
|---|---|---|
| Via capacitance | $1.41\,\varepsilon_r T D_{\text{pad}}/(D_{\text{anti}}-D_{\text{pad}})$ | Inches and picofarads; falls fast as the antipad opens |
| Isolated barrel inductance | $5.08\,h[\ln(4h/d)+1]$ nH | Assumes a remote return; usually pessimistic by several times |
| Interplane inductance | $\mu_0 h \ln(s/r)/\pi$ | The number that actually applies once ground vias exist |
| Via as coax | $(60/\sqrt{\varepsilon_r})\ln(D_{\text{anti}}/D_{\text{barrel}})$ | Per barrel; double it for a differential pair |
| Stub resonance | $c/(4\ell\sqrt{\varepsilon_r})$ | A notch, not attenuation — unrecoverable by equalisation |
| Via-to-via coupling | $5.08\,h\ln(s_1 s_3/s_2 r)$ nH | Through the shared return, not directly between barrels |
| Design rule | — | Optimise launch and barrel together; a barrel matched alone is not the best via |
Deck 4 of eleven in Signal Integrity & High-Speed Digital Design. Every figure on this page is computed by si_models/deck04 and embedded as data; nothing is typed in by hand.
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