A rail is not a voltage source, it is an impedance seen from the die. What that impedance has to be, why the number of capacitors is decided by inductance rather than by capacitance, and why adding more of them can make matters worse.
A power delivery network exists to hold a voltage steady while the current drawn from it changes. Since the current is what the load decides and the voltage is what the load needs, the property that matters is the ratio between a change in one and the change it causes in the other — which is an impedance.
Put that way, the design problem becomes a shape rather than a value. The current a digital load draws has content from direct current up to the reciprocal of its switching edge, and the network has to present a low enough impedance across all of it. No single component does that: a regulator is fast enough for kilohertz, bulk capacitors for megahertz, ceramics for tens of megahertz, and only what is on the die itself is fast enough for the switching edge.
How much charge is stored close to the load, and how much inductance lies between the store and the load. The second turns out to matter more, and it is the subject of most of this deck.
The load's own current spectrum, which belongs to whoever designed the silicon. This is why power integrity is a joint problem between the chip and the board, and why it is so often argued about across that boundary.
The scope of this deck and the three that follow is the board-level network, computed. The silicon side — regulator topologies, on-package and on-die regulation, backside power delivery, deep-trench capacitors — is treated from the chip's perspective in deck 09 of the Modern SoC Design series.
The standard first cut is Ohm's law rearranged: divide the ripple the rail is allowed by the transient current it must supply.
$$Z_{\text{target}} = \frac{V_{\text{rail}} \times \text{ripple allowed}} {I_{\text{transient}}}.$$
It is useful and it is widely misused, for a reason worth stating plainly: it is a flat number applied to a network whose impedance is anything but flat, driven by a current whose spectrum is anything but white. Meeting it at every frequency is neither necessary nor sufficient.
Notice how the target falls as systems grow. A modern accelerator rail at six-tenths of a volt and hundreds of amps needs an impedance in the tens of microhms, which is below the resistance of the copper carrying it — at which point the problem stops being a decoupling exercise and becomes a question of where the regulator physically sits.
Not necessary, because a peak at a frequency the load never excites costs nothing. Not sufficient, because a network that meets the target everywhere can still fail on a transient whose spectrum concentrates on the one peak that just scrapes under. The honest calculation is done in the time domain against the actual current profile, which is deck 12; the target impedance is what you use before you have one.
Everything awkward about decoupling follows from one fact: a capacitor is a capacitance in series with a resistance and an inductance. Below the frequency where the two reactances cancel it behaves as a capacitor and its impedance falls; above it, the inductance dominates and the impedance rises again. At the resonance itself the impedance is simply the equivalent series resistance.
Notice how little the resonance moves across four decades of capacitance once the mounting is included. The value decides where a capacitor starts working; the inductance decides where it stops. That asymmetry is the theme of the rest of this deck.
Put every branch in parallel — the regulator with its output inductance, each tier of discrete capacitors with its mounting, the plane capacitance, and the on-die capacitance behind the package inductance. The result is not a smooth curve but a sequence of dips where each tier resonates, and peaks between them where adjacent tiers fight each other.
The intuitive response to a network that misses its target is to add capacitors. Adding more of one value does lower the impedance in the band where that value is capacitive — and it sharpens the anti-resonance above it, because it lowers that branch's inductance and raises the quality factor of the parallel resonance with the tier above.
The inductance in the table on slide 03 has two parts. The part inside the component is a property of the part, and a better part buys a little. The part outside it — the loop from the pads, down the vias, to the planes and back — is a property of the layout, and above a few hundred megahertz it is usually the larger of the two.
Halving the mounting inductance by doubling the via pairs raises the useful frequency of every capacitor in the design by a factor of the square root of two, at the cost of two more holes. That is almost always cheaper than a better capacitor, and it is why decoupling rules talk about via placement rather than part numbers.
The shortest possible mounting loop goes straight down into the planes with no trace at all. Decoupling therefore moved first to the underside of the board directly beneath the package, then into the package substrate, and finally onto the die itself. Each step shortens the loop by roughly an order of magnitude and moves the frequency at which the capacitor stops working up by roughly a factor of three — and the last step is what creates the feature deck 12 is about.
Slide 05 posed a problem and did not solve it. The frequency-domain target-impedance method does, and its central observation inverts the usual intuition: the number of capacitors a board needs is not set by how much capacitance is wanted. It is set by mounting inductance.
Above their resonances, $N$ capacitors in parallel present $L_{\text{mount}}/N$ whatever their value. Meeting a target impedance at the highest frequency the discrete parts have to cover therefore requires
$$N \ge \frac{2\pi f_{\max} L_{\text{mount}}}{Z_{\text{target}}},$$
and no choice of capacitance changes that. Capacitance decides where the coverage begins; inductance decides how many parts it takes to sustain it.
Slide 05 showed that the peaks between tiers are what decide a design, and that more parts do not remove them. What does remove them is loss, and this is the point at which a habit acquired elsewhere becomes actively harmful.
The instinct to specify the lowest equivalent series resistance available is precisely wrong here. The resistance in a branch is what damps its resonance with the branch above; removing it raises the quality factor and makes the peak taller and narrower. Parts are sold with controlled series resistance for exactly this reason — a capacitor whose resistance is fixed by design rather than minimised as a by-product.
Adjacent tiers should overlap rather than leave a gap. A gap is where the anti-resonance lives, and its height depends on how wide the gap is.
Enough resistance in each branch to hold the peak down. The right amount is of the order of the characteristic impedance of the resonance being damped — a number deck 12 computes for the largest one.
Reducing mounting inductance moves every resonance up together instead of creating a new one, which is the only lever that improves the profile without introducing a new peak somewhere else.
There is a cost to damping and it is worth naming: resistance dissipates. A network deliberately given tens of milliohms of branch resistance carrying tens of amps is converting real power into heat, which is why the controlled-resistance approach is a trade against efficiency and not a free improvement.
| Quantity | Expression | Worth remembering |
|---|---|---|
| Target impedance | $V\cdot\text{ripple}/I$ | A first cut, not a sign-off criterion |
| Series resonance | $1/2\pi\sqrt{L_{\text{tot}}C}$ | Set by mounting more than by the part |
| Above resonance | $Z \to \omega L_{\text{mount}}/N$ | The value no longer matters, only the count |
| Minimum count | $N \ge 2\pi f_{\max}L_{\text{mount}}/Z_{\text{target}}$ | Set by inductance, not capacitance |
| Anti-resonance | Between adjacent tiers | More of one value sharpens it |
| Damping | $R \sim \sqrt{L/C}$ of the resonance | The lowest-ESR part is the wrong choice |
| Mounting | Halving it beats any change of value | Two more vias, not a better capacitor |
Deck 11 of eleven in Signal Integrity & High-Speed Digital Design. Every figure on this page is computed by si_models/deck11 and embedded as data; nothing is typed in by hand.
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