Every signal current is a loop, and only half of it appears on the schematic. Where the other half flows, how narrow a band it occupies, and what it costs when the board refuses to let it follow.
Charge is conserved, so current flows in loops. A driver that pushes current down a trace is also pulling an identical current back through something, and on a circuit board that something is the copper plane the trace is routed over. This is not a subtlety: the inductance and capacitance per unit length that deck 01 built everything on are properties of the loop formed by the trace and its return, not of the trace.
The consequence is that a great many signal-integrity failures are not failures of the signal conductor at all. The trace is the right width, the right length and the right distance from the plane; the plane underneath it has a gap, or a change of net, or a field of antipads punched through it, and the return current has to go somewhere else. What the signal then sees is extra inductance in series with itself, and extra coupling to whatever else is forced through the same detour.
The plane's job in this context has nothing to do with being at zero volts. A power plane works exactly as well as a return path as a ground plane does, because at signal frequencies the two are tied together by the decoupling capacitance and are the same conductor as far as the wave is concerned. What matters is continuity, not name. Deck 12 is about the frequencies where that tying-together stops working.
At low frequency the return current spreads across the plane to minimise resistance. At high frequency it does something different: it arranges itself to minimise the inductance of the loop, which means hugging the signal trace as closely as the geometry allows. The distribution it settles into is the image solution for a conductor at height $h$ above a plane,
$$J(x) = \frac{I}{\pi h}\cdot\frac{1}{1 + (x/h)^2},$$
a Lorentzian centred under the trace whose width is set by the height above the plane and by nothing else — not by the trace width, not by the frequency, not by the current. Integrating it gives the fraction of the return within any distance, and that integral is where the familiar rule of thumb comes from.
Three heights either side captures about eighty per cent, which is the number everyone quotes. Ninety per cent needs about six heights and ninety-nine per cent needs about sixty-four, because a Lorentzian's tails fall off only as the square of distance. A void in the plane well away from the trace is therefore not automatically harmless, and the "keep the plane solid for three trace heights" guideline is a statement about the bulk of the current rather than all of it.
The Lorentzian above is an analytic result derived from an image charge. The curve below it is the charge distribution computed on the reference plane by the two-dimensional electrostatic solver this series uses throughout, which knows nothing about images and simply relaxes a potential on a grid until it stops changing. They should agree, and the extent to which they do is a check on both.
The solver's trace has finite width and finite thickness where the analytic result assumes an infinitely thin filament, so the computed profile is slightly flatter across the middle. The integrated fraction within three heights is the quantity the rule of thumb is about, and the two methods agree on it closely.
The narrow band is a high-frequency phenomenon, and it is worth being precise about what "high" means here, because the changeover is lower than most people expect. Current distributes itself to minimise the total impedance of the path. At low frequency that means minimising resistance, which argues for spreading out over as much copper as possible. At high frequency the reactance of the loop dominates the resistance, and minimising inductance argues for staying directly under the trace.
Setting the two contributions equal gives the crossover. For a trace two hundred micrometres above a one-ounce plane it falls in the region of a few hundred kilohertz — far below any frequency a high-speed designer thinks about. For every signal in this series, the return current is already in its narrow band.
Because the return is directly beneath the trace and only a few trace heights wide, it is easy to protect and easy to break. Keeping the copper under a high-speed trace continuous costs nothing if it is planned and is frequently impossible to retrofit.
Two traces whose return bands overlap share return path, and shared return path is a coupling mechanism in its own right — usually a stronger one than the direct field between the traces. Deck 06 separates the two.
Now break it. A slot in the reference plane — a deliberate split between analogue and digital sections, a row of through-hole pads, a clearance for a connector — forces the return current to run to the end of the slot and back. That detour is a loop, the loop has inductance, and the inductance is in series with the signal.
A series inductance $L$ in a line of impedance $Z_0$ has the transfer function $S_{21} = 1/(1 + j\omega L/2Z_0)$, so the penalty is a low-pass filter whose corner falls as the slot gets longer. The model computes the loop inductance from the detour geometry and turns it into insertion loss.
A signal via that carries a trace from one layer to another usually changes which plane it is referenced to on the way. The signal has a via to travel down; the return current does not, unless one is provided. If the two planes are the same net, or are tied together by decoupling capacitance at the frequency in question, a stitching via placed near the signal via gives the return somewhere to go, and the penalty is the inductance of the loop between the two.
That inductance grows as the logarithm of the separation, which has a useful practical consequence: the first stitching via matters enormously and the tenth hardly at all, and moving the one you have closer is worth more than adding more further away. Symmetry helps too, because return paths on opposite sides of the signal via cancel part of each other's flux.
Computed from the fitted expressions in Johnson and Graham for one, two and four return vias. The single-via case is also derivable directly as $\mu_0 h \ln(s/r)/\pi$, and the two agree exactly — a useful reassurance that the imperial-unit form quoted in the literature is the expression it claims to be.
If the signal crosses from a layer referenced to ground to one referenced to a supply rail, a stitching via is not available — it would short the rail. The only route for the return current is through the capacitance between the planes and through whatever decoupling capacitor happens to be nearby, and that capacitor brings its own series inductance.
Above its series resonance a capacitor is an inductor, so a stitching capacitor helps over a band and stops helping above it. The resonant frequency is set almost entirely by the mounting — the loop from the pads down to the planes — rather than by the capacitance value, which is why a ten-nanofarad part and a hundred-nanofarad part mounted identically stop working at frequencies within a factor of three of each other rather than a factor of ten.
Plan the layer transitions of a high-speed net so that the reference plane either does not change or changes between two layers of the same net. That is a stackup decision, made before any routing happens, and it is close to impossible to repair afterwards. Where a change of reference is unavoidable, the stitching capacitor goes immediately beside the signal via — its usefulness is decided by the millimetres of its mounting loop, not by its value.
Two parallel planes separated by a thin dielectric form a parallel-plate waveguide. Its edges are neither open nor shorted but behave approximately as open circuits, so the structure resonates, and the frequencies at which it does are set by the board outline:
$$f_{mn} = \frac{c}{2\sqrt{\varepsilon_r}}\sqrt{\left(\frac{m}{W}\right)^2 + \left(\frac{n}{L}\right)^2}.$$
These are not a small effect and they cannot be decoupled away, because no capacitor placed at a point can suppress a mode whose wavelength is comparable with the board. They are the reason a power-plane impedance measurement, smooth and obedient up to a few hundred megahertz, breaks into a comb of peaks above it.
Below the first cavity mode a plane pair is simply a capacitor and its impedance falls with frequency as one would expect. Above it, the modes take over and the impedance becomes a series of peaks separated by nulls. The transition is abrupt and its position depends only on the outline.
This is the point at which this deck hands over to deck 12. A signal via passing through a resonant plane pair couples into it, and the energy it injects appears across the supply at every other via in the same cavity. The route from a signal transition to supply noise, and from supply noise back to jitter on another lane, is the subject of that deck.
The single most expensive mistake in this deck, and the one that produces the largest number. A twenty-millimetre slot adds enough series inductance to take more than fifteen decibels out of a ten-gigahertz signal, and no amount of equalisation at the far end recovers it.
Decide before routing which layer pairs a high-speed net may transition between. A net that stays referenced to the same plane needs no stitching at all; one that changes between two ground layers needs a via; one that changes between a ground and a rail needs a capacitor and a compromise.
Loop inductance goes as the logarithm of the distance to the return, so halving the distance buys more than doubling the count. Symmetric placement buys more again, because opposing return currents cancel flux.
A dense connector footprint or a large ball-grid array perforates the planes so thoroughly that the return path is obstructed even though no one drew a split. Deck 04 computes the antipad sizes this needs, and they are large.
| Quantity | Expression | Worth remembering |
|---|---|---|
| Return-current density | $J(x)=\dfrac{I}{\pi h}\dfrac{1}{1+(x/h)^2}$ | Width set by height above the plane, nothing else |
| Fraction within $\pm kh$ | $\frac{2}{\pi}\arctan k$ | 80% at $3h$, 90% at $6.3h$, 99% at $64h$ |
| Stitching-via inductance | $\mu_0 h \ln(s/r)/\pi$ | Logarithmic in distance: move it closer rather than adding more |
| Slot-crossing penalty | $S_{21}=1/(1+j\omega L/2Z_0)$ | A 20 mm slot is a low-pass filter with a corner around 1 GHz |
| Cavity modes | $f_{mn}=\frac{c}{2\sqrt{\varepsilon_r}}\sqrt{(m/W)^2+(n/L)^2}$ | Set by the outline; decoupling cannot remove them |
| Resistive-to-inductive crossover | $f \approx R_\square/(2\pi L_{\text{loop}})$ | A few hundred kilohertz; every signal here is above it |
Deck 2 of eleven in Signal Integrity & High-Speed Digital Design. Every figure on this page is computed by si_models/deck02 and embedded as data; nothing is typed in by hand.
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