Co-Packaged Optics and Optical I/O

Topics We'll Cover

• Why Move the Optics Into the Package
• Anatomy of a Co-Packaged Switch
• The OIF Agreements
• What Switch Vendors Have Announced
• Interactive: Energy Along the Electrical Path
• Optical I/O for Compute
• Serviceability and Reliability
• Heat Next to the ASIC
• Fibre at Scale
• Near-Packaged Optics and Other Middle Grounds
• When CPO Wins, and When Pluggables Do
• What to Take Away

Why Move the Optics Into the Package

In a pluggable design each lane leaves the switch die, crosses the package and many centimetres of board to a faceplate cage, and is re-timed in the module (deck 01). Co-packaged optics (CPO) puts the optical engine on the switch's own package substrate, millimetres from the die, so the electrical channel nearly disappears.

• Shorter channel, simpler SerDes. Less loss to equalise means less equaliser, and no module DSP at all: the energy that was spent driving and recovering a lossy trace twice (in the switch and in the module) mostly goes away. A SerDes IP vendor contrasts a 15 dB VSR channel with a 28 dB long-reach channel with two connectors (Synopsys, vendor article).
• The faceplate stops being the limit. Bandwidth leaves the box as fibre, not as module cages, and module heat no longer has to leave through the faceplate (deck 01, slide 11).
• The cost is everything a pluggable made easy: replacing one port's optics, mixing optics types, and keeping lasers away from a hot ASIC (slides 07–09).

Anatomy of a Co-Packaged Switch

• Optical engines are silicon photonic chips with their drivers and TIAs (electronic–photonic integration), placed around the ASIC's edge where its SerDes are. Broadcom's 51.2 Tb/s design uses eight 6.4 Tb/s engines (slide 04).
• Lasers stay outside in front-panel modules and feed continuous-wave light to the engines over polarisation-maintaining fibre (external laser source): lasers are the least reliable and most heat-sensitive part, and the front panel is the coolest place in the box.
• Fibre runs from each engine to faceplate connectors (slide 09); the engines' fibre attach is the packaging problem of OptSiP 03 repeated many times on one substrate.

The OIF Agreements

• Why agreements matter here: without them, every CPO switch is a single vendor's closed system of ASIC, engines, lasers and fibre. Defining the electrical lane, the module and the laser lets switch, engine and laser makers work separately, which is what MSAs did for pluggables (deck 01).
• The silicon photonics view of the external laser is in OptSiP 03, slide 03.

What Switch Vendors Have Announced

• Read these as vendor claims. Each compares against the vendor's own choice of pluggable baseline, which the releases do not fully specify; “optical interconnect power” excludes the switch core. They agree in direction, not in a number you can design with.
• The interactive on the next slide rebuilds the comparison from per-stage energies you can set, so you can see which assumptions give 50% and which give 70%.

Interactive: Energy Along the Electrical Path

Energy per bit for one switch port, added up stage by stage for three architectures: a DSP-retimed pluggable (host VSR SerDes, module DSP, optics, laser), a linear-drive pluggable (no DSP, some extra host effort) and co-packaged optics (a short XSR lane, optics, external laser). Every default is illustrative, chosen to be consistent with deck 01's interactive (a DSP module near 11 W at 800G); set them from a datasheet to test a vendor's claim.

Limits: one direction of a link counted once; the same optics and laser energy for all three, though CPO engines can use lower-swing drivers and different lasers; the switch core's power is excluded, as in the vendors' “optical interconnect power”. Power is energy per bit × capacity.

Optical I/O for Compute

The same idea applied to processors: an optical chiplet in the GPU, CPU or memory package replaces long electrical links for scale-up and memory traffic (deck 04). Unlike switch CPO, which serves standard Ethernet ports, optical I/O chiplets often run many wavelengths at modest rates per wavelength.

• Many wavelengths, modest rates: 64 lanes at 32 Gb/s (Intel) is the dense-WDM, ring-based architecture of OptSiP 03, slide 12, with its comb or multi-wavelength sources (multi-wavelength sources) and ring tuning (thermal tuning).
• The chiplet interface: UCIe, the die-to-die standard released in March 2022, includes an off-package usage model through retimers onto other media, optics among them (UCIe Consortium).
• The photonic link module of the Compute in Transit series takes a different path: a pluggable that also computes on the data it carries.

Serviceability and Reliability

• The case for lasers outside: a trade-press analysis puts typical transceiver failure rates at about 200 FIT and argues that clusters with a million links need lasers at least a hundred times more reliable (Herrick, Compound Semiconductor). No peer-reviewed external-laser FIT figure was found for this deck.
• Field evidence so far is vendor-reported: Broadcom reports about one million cumulative 400G-equivalent port device hours of flap-free CPO operation at Meta, in a high-temperature lab, and a 65% reduction in optics power (Broadcom, October 2025).
• Link flaps and failures matter because a training job stops when any link in it fails (deck 04, slide 10).

Heat Next to the ASIC

• Optics dislike heat and the switch die makes a lot of it. Silicon photonic devices drift with temperature at about 72 pm/K for a typical silicon wire (OptSiP 01, slide 10), and germanium detectors leak more current when hot (dark current).
• Ring-based engines need active tuning to follow the substrate's temperature (thermal tuning); Mach–Zehnder-based engines tolerate drift better at the cost of size and drive power (OptSiP 02, slide 04). The trade is tuning power and control against footprint.
• Lasers are kept off the package for this reason (slide 02): laser efficiency falls and wavelength drifts as temperature rises (wall-plug efficiency).
• Cooling changes with it: NVIDIA's Quantum-X Photonics switch is liquid-cooled (slide 04). Heat that used to leave through hot faceplate modules now leaves through the package's cold plate along with the ASIC's.

Fibre at Scale

Arithmetic: lanes ÷ wavelengths per fibre, doubled for the two directions; laser feed fibres are extra. The OIF 3.2T module offers both DR4 and FR4 optics (slide 03).

• Fibre count is a packaging cost: every fibre must be aligned to an engine at sub-micrometre tolerance (packaging) and routed to the faceplate. WDM trades fibres for lasers, multiplexers and tuning (bandwidth scaling).
• Detachable fibre interfaces let engines be tested before fibre is committed and fibre be replaced later: SENKO and GlobalFoundries showed a wafer-level detachable fibre interface for CPO at ECOC 2025 (SENKO; vendor announcement).
• Laser fibres must hold polarisation, because silicon photonic circuits are polarisation-dependent (OptSiP 01, slide 03).

Near-Packaged Optics and Other Middle Grounds

• OIF's XSR+ agreement names multi-chip modules, CPO and near-packaged optics as its intended uses (slide 01): the electrical lane is defined once and used at several distances.
• Each step towards the die trades field replaceability for electrical energy and density; which step is right depends on how much bandwidth must leave the chip and how often its optics fail.

When CPO Wins, and When Pluggables Do

These are the arguments as engineering trade-offs, not a forecast; the vendor claims of slide 04 are the evidence so far, and they come from the companies selling CPO.

What to Take Away

• CPO shortens the electrical channel from a faceplate host trace (VSR: up to 16 dB at Nyquist) to millimetres on the package (XSR: up to 50 mm; XSR+: up to 13 dB bump to bump), removing the module DSP and most of the equalisation.
• OIF has defined the pieces: a framework (2022), a 3.2T module (2023), the external laser module ELSFP (2023, revised 2025) and the XSR+ lane (2024).
• Vendors claim 50–70% lower optical interconnect power (Broadcom) and 3.5× better power efficiency (NVIDIA) against their own pluggable baselines; the interactive shows how such numbers follow from per-stage assumptions.
• The price is serviceability, heat and fibre: lasers moved to the faceplate, known-good engines, detachable fibre and tuning against a hot substrate.
• Optical I/O chiplets bring the same idea to processors, with many wavelengths at modest rates (Intel: 64 × 32 Gb/s; Ayar Labs: 4 to 8 Tb/s), at vendor-claimed energies near 5 pJ/bit.
• Next: deck 03 switches the light itself.