Live, animated companion: AI Accelerators Explained (Hardware track) — ten chapters, each built around an animation computed by the site’s model. Each deck below links its chapters; every specification’s source and access date is on the specifications page.
Presentations in This Series
- The Design Space and the Memory Wall →The three axes and the eight families; the running workload (a Llama decoder); GPUs and systolic designs as the baseline; capacity as the first trade; every family side by side; bounds against published figures; what the families are converging on.
- SRAM Machines: Wafers, LPUs and IPUs →Why SRAM; a wafer of 84 dies and how defects are survived; models split across wafers and weight streaming; the GroqChip's static schedule and a 576-chip chain; what the published speeds say about the bound; the IPU's bulk-synchronous tiles.
- Dataflow, Meshes, Edge and In-Memory →A layer kernel by kernel vs fused; three tiers of memory and the SN40L paper's measured speed; a mesh of cores split over cards; a batch-1 decode at narrower weights on an NPU or FPGA; a decoder on phase-change crossbars, and what it costs in capacity and precision.
Bounds, said plainly. The model computes bounds from vendors’ stated bandwidths and peak rates. For chips that read their weights from DRAM the bound is close to what systems achieve; for SRAM designs the published speeds are a small share of it, and the decks say so. No vendor claim is used as an input.
The two baseline families in depth: NVIDIA GPU Architectures (live) and Google TPUs (live). Computing with light: Fourier Optics for Inference.