Which AI workloads could a future dense, 3D-stacked photonic chip run well, and under what conditions? The future system its developer has described in public stacks a photonic layer on its logic. A simulator now models it: throughput against an all-digital ASIC, energy per useful operation, laser and heat limits, calibration, and an approximate mode that chains optical stages for FFT- and AI-style work. This deck asks what precision AI formats need, what the chip's approximate mode delivers, what each costs in energy, and runs the candidate workloads through one screen. Every number comes from the simulator's data, from tested code in this repository, or from a cited source; every mechanism has a figure driven by a tested model.
The chip first, then the four bills it must pay (memory, precision, energy, physics), then each AI workload through one screen.
Concepts used here, and where they are explained. Each links to a glossary entry in this series glossary or a sister series'.
Decks 01–03 asked what a Fourier-optical engine costs in general; deck 04 and the simulator after it asked what today's pluggable photonic link module (arXiv:2608.21536) does. What changed: the simulator (plms 0.3.0) now models the future system its developer has described in public, a photonic layer stacked on its logic, and runs it against an all-digital ASIC of the same logic and of the same silicon. This deck asks which AI workloads that chip could run well, and under what conditions.
Four optical channels on a QSFP56 module beside a host FPGA; the devices “can operate at 14 GBaud/s (28 Gbps PAM4)” (the paper, §II); the series' simulator found it slower and far costlier in energy than the FPGA alone: 35779 pJ against 56 pJ per full-width transform. modelled
U optical transform units bonded onto the logic that drives them, with W wavelengths, so there is no package port between optics and logic: the 3D stacking is the developer's public statement. The paper's §V describes a monolithic chip, “a 112 GBaud/s Photonic Integrated circuit (PIC)” with “custom high-speed logic operating at 28 GHz”; the simulator takes the 112 GBd and 28 GHz from there. Two modes: exact (integers, for FHE and PQC) and approximate (a few effective bits, for FFT- and AI-style work). public-statement paper
What the simulator models and where the full method is explained: the explainer site's method and its Part II chapters. This deck uses its results; it does not re-derive them.
With the simulator's illustrative parameters, no AI workload screened here pays on this chip. Exact mode is held at the memory wall (1×) and at most near 1.1× when compute binds; approximate mode keeps about 3.2 effective bits and costs 32× a digital butterfly of matched precision. The last slides say what would have to change, by how much.
Each item is tagged as the simulator tags it: public-statement is what the developer has said in public about its next system; paper is the module paper's section V projection; illustrative is an engineering inference, not a measurement.
One value's path, step by step (systemPath); the simulator's model of it is in the explainer's stacked-chip chapter. The mode changes what crosses the bond: in exact mode each 59-bit operand goes through as bit planes, one per pass; in approximate mode the operand is one symbol and the light can go on through several stages before it is read out.
| Item | Default (swept) | Tag |
|---|---|---|
| Photonic layer 3D-stacked on the logic (hybrid bonding). The developer's public statement, not the paper: §V describes “a monolithic silicon photonic chip” | 30 fF receiver, against 300 fF packaged | public-statement |
| U units, each a 4-point optical transform | 64 (4–4,096) | illustrative |
| Symbol rate B | 112 GBd (14–112) | paper |
| W wavelengths sharing each unit's mesh | 4 (1–8) | illustrative |
| Drivers, TIAs, decisions and reduction in the logic underneath; custom high-speed logic at 28 GHz (§V) | 100 mm² of logic (5–200) | paper illustrative |
| One external 20 dBm laser, split on-chip | wall-plug 0.15 | illustrative |
| Thermo-optic phase shifters, 18 per unit plus 8 per wavelength | 10 mW per π (2–30, MEMS, non-volatile) | patent illustrative |
| One optical-electrical crossing, either direction | E_conv = 0.5 pJ/bit (0.05–2) | illustrative |
The simulator times a CKKS bootstrap kernel by kernel on the chip and on two all-digital ASICs: one with the same logic, one that spends the photonic layer's silicon on more logic. With today's HBM the chip and the ASIC take the same time: 52.97 ms (sparse16) and 70.51 ms (full14), 1×, because HBM binds and the optimal split sends nothing through the optics. When compute binds (unconstrained HBM, 10 mm² of logic), exact arithmetic caps the gain near 1.1×, since the optics remove only the modular adds, and the same silicon spent on logic is faster: the best point reaches 0.9163× of the equal-silicon ASIC.
Data: the simulator's e12, explained in the break-even-at-scale chapter (1,728 swept points per workload in the compute-bound regime; the left chart is its logic-area × HBM sweep). Ceilings for sparse16 at 59 bits: exact 1.1×, NTT-free 2.754×. modelled
Exact mode converts at every stage. Each radix-4 stage is decided, recombined from its bit planes and reduced mod p before its twiddle multiply, so every operand crosses out of the light and back once per stage, as 59 bit planes. Approximate mode carries one operand per symbol and chains S stages optically before the light is read out, so the conversions are shared by S stages. The animation runs a 4,096-point FFT's 6 radix-4 stages; choose the mode and S.
Frames from fftChain(mode, S) (the simulator's approximate-mode chapter has the method); the energy figures in the caption come from the simulator's e16 table (8-bit converters, U = 64, 4 λ, 112 GBd). From S = 1 to S = 6 the energy per butterfly-stage falls from 34.11 to 6.929 pJ (4.923×), and the rate is 59× the exact-mode rate. modelled
The simulator runs the chained FFT by Monte Carlo: DAC, S lossy unitary stages with phase error, receiver noise at the design SNR (27.47 dB per level step), ADC. With 8-bit converters and 1 dB per stage the output keeps 2.74 effective bits at S = 1 and 3.198 at S = 6: fewer conversions add less noise. At 3 dB per stage the loss wins instead, 2.445 falling to 1.268. Better converters barely help, because the receiver noise sets the ceiling: 16-bit converters reach 3.22 at S = 6, and only a 40 dB receiver SNR lifts it to 4.691.
Data: e16's S × converter-ENOB grid (4,096-point FFT). The simulator's measure is (SNR − 1.76)/6.02 of the whole FFT's relative error; the right-hand readout restates it in the series' ENOB (slide 06 explains the difference). modelled
These bits are for one wavelength. A mesh's phases scale with wavelength, so when W wavelengths share one mesh every channel away from the centre sees a slightly wrong transform. On a 200 GHz grid around 1310 nm the worst channel keeps 2.731 bits at S = 1 and 3.19 at S = 6 with 4 λ (2.74 and 3.198 alone), and 2.558 at S = 6 with 32. Exact mode barely notices: the worst of 16 channels is 0.01558 off the ideal transform and loses 0.04545 dB of margin. See the explainer's wavelengths chapter. modelled
A float workload does not need exact results; the analogue chain need only match the error its number format already makes. The series' rule (deck 01, slide 17) gives the ENOB that matches a format's own rounding error on a long convolution: relative RMS error = crest × 2−ENOB × 2/√12. analysis/precision_needed.py regenerates the series' signal and reproduces its three values exactly (BF16 10.3, INT8 8.0, FP8 E4M3 6.3) before computing the new ones.
| Format | Scaling | Rounding error | ENOB needed (series rule) | Effective bits (e16 measure) |
|---|---|---|---|---|
| BF16 | the series' | 0.00164 | 10.32 | 8.96 |
| INT8 | per tensor | 0.00834 | 7.98 | 6.61 |
| FP8 E4M3 | per tensor | 0.0261 | 6.33 | 4.97 |
| FP8 E5M2 | per tensor | 0.0536 | 5.29 | 3.93 |
| NVFP4 | E2M1, block 16, E4M3 scale (NVIDIA) | 0.0931 | 4.50 | 3.13 |
| INT4 g32 | one scale per 32 values | 0.0986 | 4.41 | 3.05 |
| FP4 E2M1 | per tensor | 0.114 | 4.20 | 2.84 |
| MXFP4 | E2M1, block 32, E8M0 power-of-two scale (OCP MX v1.0) | 0.118 | 4.16 | 2.79 |
| INT4 | per tensor | 0.151 | 3.80 | 2.44 |
Needed (bars) against available (lines: e16 at S = 1 and S = 6, 1 dB per stage, 8-bit converters; S = 6 at 3 dB). Both are converted from the same relative error, so they share an axis; the two measures differ by a crest term of 1.37 bits for this signal. computed modelled
FP4 and INT4 have never been computed in the series: FP4 E2M1 needs 4.20 ENOB and INT4 3.80 by the series' rule. Approximate mode's best, 3.198 effective bits, is on the scale of FP4's own rounding (2.84 to 3.13 in the same measure), and well short of FP8 (4.97) and BF16 (8.96). Matching is not enough on its own: the chain's error adds to the format's, so an FP4 workload on this chip would carry about twice the error variance of FP4 alone. Our numbers, from analysis/out/results.md.
Exact mode costs 485.9 pJ per 59-bit 4-point transform against 32.35 pJ in the ASIC. The 708 crossings alone cost 354 pJ; the optics replace only the cheapest part of a butterfly, its modular adds. Approximate mode at S = 6 costs 6.929 pJ per butterfly-stage, against 0.7188 pJ for a digital 8-bit complex butterfly (12 multiplies, 22 adds) and 0.2141 pJ for one at the precision the optics actually deliver (digital energies from “Horowitz, ISSCC 2014, 45 nm”, via Han et al. Table I: 32-bit add 0.1 pJ, multiply 3.1 pJ, scaled by 0.25). Its throughput is 59× the exact-mode rate, but energy per useful operation is 32× the digital figure.
The bar stacks the simulator's components (laser at the wall, phase shifters, conversions, recombination or boundary twiddles, logic) one per step; the digital bar is beside it (method: the energy chapter). HBM traffic is the same for both designs and is left out; per bootstrap it adds 1.07 J to each (sparse16). modelled
Per butterfly-stage, with S stages chained, b converter bits and R = U·W·B·0.95 symbol slots per second, the simulator's energies reduce to one formula (analysis/breakeven.py, which reproduces every row of its table):
E = (8·b·E_conv + twiddles(b)) / S + (n_lasers·P_laser/η_wall + U·(18 + 8W)·P_π) / R
It wins when E falls below a digital butterfly at the bits the optics deliver. The second term is static: laser and heaters, paid whatever S or E_conv. Where it never pays: whenever that static term alone exceeds the digital butterfly. At the defaults the laser alone is 0.3182 pJ and the heaters 1.175 pJ, against 0.2141 pJ: no conversion energy, however small, rescues it.
The matched-precision digital butterfly uses ceil(effective bits) from e16 for the chosen S and b. The crossing and twiddle terms are this deck's reconstruction: they reproduce the simulator's table exactly, but the simulator does not state which values make up its 8·b converted bits. computed illustrative
Light. One 20 dBm laser feeds about 20 unit-wavelengths at a 6 dB margin (U × W = 20 at 4 λ, 26 at 1 λ; 8 and 12 at 10 dB), at 112 GBd with a 30 fF receiver. So the default chip needs 13 lasers, and laser power grows with U × W. Heat. Thermo-optic phase shifters at 10 mW per π hold 0.5 W per unit (1.25 W/mm²); they alone reach the 500 W cap at U = 1000.
Data: e14 (the light-and-heat chapter). The laser path loses power in the coupler, WDM, splitter tree, propagation and modulator; the margin is how far every noise term can grow before the worst output misses the error target. modelled
| Laser [dBm] | Max U×W at 6 dB | Max U×W at 10 dB |
|---|---|---|
| 13 | 4 | 0 |
| 17 | 8 | 4 |
| 20 | 20 | 8 |
| 23 | 36 | 16 |
| 27 | 92 | 44 |
A stronger laser feeds more units but costs proportionally more at the wall: across these five lasers the laser energy per butterfly-stage stays between 0.3125 and 0.3925 pJ (breakeven.py), all above the 0.2141 pJ digital figure of slide 07.
The light budget holds: with the wavelength error included, one laser still feeds U × W = 20 at 4 λ and 6 dB. Two other limits come first. The 5 µm rings' free spectral range, 14.01 nm, holds at most 8 channels at 200 GHz. The signal and LO paths must match to 0.08156 µm, or the LO must be trimmed per channel (an unmatched 1 mm rotates the edge channel of 16 × 200 GHz by 122.6 rad). Heaters cannot calibrate the error away: it is a tilt across the band, and one set of phases serves every channel. A mesh per wavelength removes it, but at 4 λ and U = 64 that takes 64 mm² and 66.56 W of heaters, against 25.6 mm² and 32 W shared. See the explainer's wavelengths chapter. modelled
The logic underneath heats the optics. An idle-to-busy step of the logic (0.5 W/mm²) spans 3.192 K across U = 64 and moves heater phases by up to 0.05947 rad; no unit passes the error target until 2 W/mm². Calibration scales worse: with a controller serving 4 units at once, at least 0.9 of units stay in service up to U = 1,024 at 0.03 rad/√s of drift and U = 256 at 0.1 rad/√s; start-up calibration takes 4096 s for U = 16,384.
e14's temperature map as the simulator exports it, 0.05 mm cells; hot spots of the logic show as warm patches. modelled
Calibration figure: each step is one swept U (e15's queueing result, M/M/P//U; the calibration-at-scale chapter); the grid shows the share of units in service, never colour alone (hatched = out of service). modelled
The Compute in Transit series screens candidates with five tests (CiT_01, slide 10). On a stacked chip the data no longer passes through a link, so each test reads a little differently; this deck adds two from slides 06 and 08.
| # | Test | On the stacked chip | Decided on |
|---|---|---|---|
| 1 | Bottleneck | Is the transform a large share of the workload's time (Amdahl)? Is memory not binding? | Slides 03, 13 |
| 2 | Operations | Is the work a 4-point transform chain (FFT, NTT, convolution), or can it become one? | Slide 02 |
| 3 | Budget | Does the logic keep up? Exact mode leaves the multiplies to the logic; approximate mode leaves the twiddles at block edges. | Slides 03, 04 |
| 4 | Noise or exactness | Does it tolerate analogue noise, or need exact integers? | Slide 04 |
| 5 | Placement | Is the data already on the chip, or must it cross a link to get there? | Slide 15 |
| 6 | Precision | Does its format need no more than the chain delivers (about 3.2 effective bits)? | Slide 06 |
| 7 | Energy | Does it beat a digital unit at matched precision? | Slide 08 |
Test 7 fails for every candidate at the simulator's illustrative parameters (slide 08), so the verdicts on the next slide say which test each candidate fails first, and which would remain if the energy terms changed.
| Candidate | 1 | 2 | 4 | 6 | 7 | Verdict and reason |
|---|---|---|---|---|---|---|
| Fourier mixing: FNet, Hyena | ✗ | ✓ | ✓ | ✗ | ✗ | no The transform is 0.09% (FNet) and 0.20% (Hyena) of prefill FLOPs: at most 1.002× if it were free. BF16 needs 8.96 effective bits against 3.198. |
| Block-circulant weights | ✓ | ✓ | ✓ | ~ | ✗ | not as modelled The only large share: 84.54% with the LM head on the last token, Amdahl 6.5× (speculative at LLM scale). Needs FP4-level tolerance and the energy conditions of slide 16. |
| FP4 (E2M1) MAC (paper §V) | ? | ✗ | ? | ~ | ? | unknown A projection for a future chip, not a measurement; a MAC, not a transform. Whether it is analogue is unknown. If it is, and if it is block-scaled like NVFP4 (our reading; the paper says only “FP4 (E2M1) MAC”), matching NVFP4's rounding needs 3.13 effective bits before any accumulation error. |
| Low-bit KV ranking (PRISM-style) | ~ | ✗ | ✓ | ✗ | ✗ | no, as modelled Ranking tolerates noise: “only rank order matters (relaxing precision to 4-6 bits)” (PRISM). But it is a dot product, and 4 to 6 bits exceed 3.198. |
| KV compression (KIVI, KVQuant) | ~ | ✗ | ✗ | – | – | no Quantisation needs scaling, comparison and rounding, not a transform. |
| Training traffic: 2-bit deltas (MuLoCo), DeMo's fixed band | ~ | ✗ | ~ | – | – | no Link traffic, not on-chip compute; the fixed band, the only transform route, ends more than a nat above top-k (CiT_04). |
| FHE and PQC NTTs (exact mode, for contrast) | ✗ | ✓ | ✓ | n/a | ✗ | no gain modelled The developer's stated first market. HBM binds (1×); compute-bound, 1.099× over equal logic and 0.9163× of equal silicon; 485.9 against 32.35 pJ. |
✓ passes, ✗ fails, ~ borderline or conditional, ? unknown, – not reached. Tests 3 and 5 are omitted from the columns: test 3 passes for every candidate that passes test 2, and test 5 matters only for the traffic rows. The verdicts are this deck's judgement from the numbers cited; none is a measurement.
Amdahl decides first. In a Llama-3-8B-shaped model at a 2,048-token prompt, Fourier mixing is a sliver of the work: an FNet-shaped mixer (FNet) is 0.09% of prefill FLOPs, Hyena (order 2; arXiv:2302.10866) long convolutions 0.20%. Only when the weights themselves become transforms (block-circulant, as in CirCNN, arXiv:1708.08917) does the share matter: 13.99% with the LM head charged for every token, 84.54% with it on the last token only, as serving engines do.
One variant per step, from the series' FLOP ledger (flop_share.py, prompt 2,048). Bound = 1/(1 − share). Even the circulant case's 6.5× assumes the optics are free and exact enough; at 3.2 effective bits, and 32× the energy of a matched digital butterfly, neither holds. computed
The module paper projects an FP4 MAC on a future link: “45 GFLOPS of FP4 (E2M1) MAC is enabled on a 112 GBaud/s photonic transceiver link for an additional 1 pJ/bit” (the paper, §V) paper. That is a projection for a future chip, not a measurement. The paper adds “Since the core compute technology is passive…”, but not whether the MAC itself is analogue and optical or digital in the logic. The two cases lead to different answers. The paper says only FP4 (E2M1); block scaling, below, is this deck's reading.
FP4 E2M1 has eight magnitudes, 0 to 6 (drawn from FP4_GRID, tested in Python). NVFP4 “applies a fine-grained E4M3 scaling factor to each 16-value micro-block” with “a second-level FP32 scalar applied per tensor” (NVIDIA); MXFP4 uses blocks of 32 with an E8M0 power-of-two scale (OCP MX v1.0). Whether the projected MAC is block-scaled is not stated: our reading.
Unknown, then, and it is the first question for the developer (slide 18). FP4 is not a precision the series has used before; this deck computed it on slide 06.
| Method | What it does (as cited) | On this chip |
|---|---|---|
| PRISM (arXiv:2603.21576) | A photonic similarity engine for KV block selection: “only rank order matters (relaxing precision to 4-6 bits)” | Ranking is a dot product against the query; 4 bits already exceed the chain's 3.198 |
| KIVI (arXiv:2402.02750) | “quantizing the key cache per-channel and the value cache per-token to 2bit” | Quantisation: scaling and rounding, no transform |
| KVQuant (arXiv:2401.18079) | “< 0.1 perplexity degradation with 3-bit quantization”; “LLaMA-7B model with 10M context length on an 8-GPU system” | Quantisation, as above |
| MuLoCo (arXiv:2505.23725) | v1: “aggressively compress the communicated delta to 2-bits with next to no performance degradation”. The current v3 revises this: “Both MuLoCo and DiLoCo achieve lossless 4-bit quantization”; at 2 bits plain linear quantisation is impractical and statistical quantisation is needed | Traffic between workers: a link, not on-chip compute |
| DeMo (arXiv:2411.19870) | DCT on chunks of up to 64×64 (64 for 1-D), top-32 per chunk (its code's defaults) | Top-k is a decision, not a transform; the fixed band that would replace it fails (below) |
A 15.8M-parameter GPT trained on TinyStories with eight simulated workers: top-k DeMo ends 0.139 above AdamW, and “every fixed band ends more than a nat above top-k”; the low band keeps 0.013 of the momentum's energy against 0.643 for top-k. The data-independent band an optical transform could apply is the one that fails.
Placement settles the rest. These are movements of data between chips; a stacked chip computes on data already beside it. The link module of decks 01–04 was the device for traffic, and CiT_01 to CiT_04 screened it.
Five conditions, each with its number from this deck, for an AI workload to pay on this chip. All must hold together.
| # | Condition | Number | In the public roadmap? |
|---|---|---|---|
| 1 | Memory must not bind | With 819 GB/s of HBM the chip equals the ASIC (1×); even unconstrained, exact mode caps near 1.1× | No: the HBM generation is not stated |
| 2 | Static light and heat below a digital butterfly | Laser 0.3182 + heaters 1.175 pJ against 0.2141; needs wall-plug efficiency of 0.4302 (modelled 0.15) and near-zero hold power (MEMS or non-volatile: 0.3183 total) | No: laser efficiency and phase-shifter technology are not stated |
| 3 | Conversions nearly free | Even with free heaters and a lossless laser, E_conv ≤ 0.005926 pJ/bit at S = 6 (modelled 0.5) | Partly: stacking cuts the receiver to 30 fF; the energy per crossing is not stated |
| 4 | A workload that is mostly transform and tolerates FP4-level error | Transform share like circulant weights' 84.54%; about 3.13 effective bits (NVFP4's rounding, if block-scaled: our reading) against 3.198 available | Partly: “45 GFLOPS of FP4 (E2M1) MAC” “for an additional 1 pJ/bit” is projected (§V) paper; its analogue-ness is unknown |
| 5 | If wavelengths share a mesh: achromatic phases, or one mesh per wavelength modelled | With 4 λ on one mesh the worst channel keeps 3.19 bits at S = 6 (3.198 alone), with 32 only 2.558; a mesh per wavelength removes the error but at 4 λ and U = 64 takes 64 mm² and 66.56 W of heaters, against 25.6 mm² and 32 W shared | No: the wavelength plan and how the mesh handles it are not stated |
Against the 8-bit digital butterfly instead of a matched one, the bar is lower but still steep: with MEMS phase shifters E_conv would need to be 0.02787 pJ/bit. These are our numbers (analysis/out/results.md), on the simulator's illustrative parameters.
| Question | Why it matters |
|---|---|
| What is the native precision of the FP4 MAC, and is it analogue? | Decides whether slide 14's left or right column applies |
| Which HBM generation and bandwidth? | At 819 GB/s the chip equals the ASIC (slide 03) |
| What is the conversion energy per crossing, in pJ/bit, both directions? | The simulator assumes 0.5; break-even needs about 0.005926 (slide 16) |
| Which phase-shifter technology, at what hold power? | Thermo-optic heaters cost 1.175 pJ per butterfly-stage, more than the whole digital butterfly |
| Laser wall-plug efficiency and fan-out per laser? | The laser alone exceeds a matched digital butterfly at 0.15 |
| How many stages can approximate mode chain, at what loss per stage? | At 3 dB per stage, chaining loses bits (2.445 to 1.268) |
| How many wavelengths share each mesh, and are its phases achromatic or trimmed per channel? | With 32 λ on one mesh the worst channel falls to 2.558 bits at S = 6; a mesh per wavelength costs area and heater power (slide 16) |
| Which AI kernels are targeted, and at which number format? | The screen finds none at FP8 or above |
data/plms_v0_3/Every modelled number. Presented in full on the explainer site: method, and the chapters linked from slides 02–10.data/plms_v0_4/The plms 0.4 notes on slides 05, 09 and 16. Sections 7 and 12–16 are unchanged in 0.4.0. Explained in the wavelengths chapter.data/foptinf_analysis/Amdahl shares and the series' ENOB rule.analysis/ in this repository: precision_needed.py, breakeven.pyEvery computed number; results in analysis/out/results.md.sources/quotes.md)mxfp4().| Parameter | Default | Tag |
|---|
Generated from the simulator's future-chip assumptions table (data/plms_v0_3/results_extract.md); the deck's own reconstruction of the approximate-mode crossing count is tagged illustrative on slide 08.