Fourier Optics for Inference — Presentation 04

Inside a Photonic Link: Modulators, Detectors and Constellations

The hardware primer for the photonic link module of deck 01 (arXiv:2608.21536): light as a carrier that a photodiode sees only as power; the Mach–Zehnder modulator and its three bias points, and why quadrature suits unsigned bits; the textbook IQ modulator; holding a bias with dither and lock-in; direct against coherent detection with a local oscillator and a balanced pair; one input vector followed through the whole chain as constellations; the DFT's PAM5 and 3×3 alphabet and its packing into PAM4; calibration, where input phase errors distort and output errors rotate; the transimpedance amplifier, the noise budget and lane skew; and what a simulator needs from all of it. Every concept has a figure, and every mechanism an animation driven by a tested model.

MZM bias points Coherent detection Constellations PAM4 TIA Calibration Skew
Bits → Driver + MZM → Optical FT → LO + balanced PDs → TIA → PAM4
00

Topics We'll Cover

The hardware of a photonic link module (arXiv:2608.21536, Kundu et al.), from the bits the host sends to the bits it gets back. FOptInf 01 introduced the module; this deck explains each part of its signal chain, with the signal drawn as a constellation at every stage. Click a block to jump to its slide.

FPGA TXbits, NRZ driverswing / Vπ MZMquadrature phaseshifters optical FT4-point DFT 2×2 + LOprojection balancedPD pair TIAlinear PAM4clip + code FPGA RXdecode light(laser split 7 ways) FPGA TX: bits, NRZ driver: swing / Vπ MZM at quadrature phase shifters optical FT: 4-point DFT 2×2 coupler + LO balanced PD pair TIA (linear) PAM4: clip + code FPGA RX: decode

The module's signal chain, as its paper describes it (the PAM4 clipping is this deck's reading, slide 12). Highlighted: the two optical stages that compute (the modulators write the data onto light; the optical Fourier transform mixes the four lanes). Everything after them reads the result out.

Labels used on every slide: paper stated in arXiv:2608.21536; patent stated in a patent the paper cites; textbook standard physics or a published paper; derived arithmetic shown on the slide; inference this deck's reading, not stated by any source; illustrative a parameter chosen for the model, not measured. Numbers come from analysis/link_hw/results.md.

01

Light Is a Carrier; a Photodiode Sees Only Power

Light at 1550 nm is a carrier at about 193 THz. Its field E(t) = A·cos(2πft + φ) has an amplitude A, which can be negative, and a phase φ, exactly like an RF carrier. No electronics can follow 193 THz: a photodiode's current is proportional to the power |E|², averaged over many cycles. textbook

Top: a field whose amplitude flips from +A to −A halfway (the carrier drawn absurdly slowly, a few cycles where light has billions). Bottom: what a photodiode reports, the power averaged over the carrier cycles, A², the same on both halves. The sign, and with it any phase, is gone.

OpticsRF and electronics equivalent
LaserCarrier oscillator
PhotodiodeSquare-law (power, or envelope) detector
Mach–Zehnder modulatorBalanced modulator: a differential pair or Gilbert cell
Bias point of a modulatorDC operating point of an amplifier or mixer
Coherent receiver with a local oscillator (LO)Mixer with an LO; homodyne = zero IF
Balanced photodiode pairSingle-balanced mixer (rejects LO feedthrough and LO amplitude noise)

Concepts used here, and where they are explained. Each links to a glossary entry: this series glossary, or the glossaries of LLM Inference Simulators, FHE Accelerator Simulators and the Simulation Engineering Toolkit for concepts those series already explain.

02

The Mach–Zehnder Modulator

Phase is easy to change in silicon; amplitude is not. A voltage across a pn junction in the waveguide moves free carriers and shifts the refractive index (plasma dispersion: tens of GHz, but weak); a heater does the same through the thermo-optic effect (strong, but microseconds). A phase change alone is invisible to a photodiode. An interferometer makes it visible: split the light into two arms, shift their phases, and recombine, so the fields add. textbook

Δφ = φbias + π·V/Vπ    Eout = Ein·cos(Δφ/2)    Pout = Pin·cos²(Δφ/2)

Each arm carries half the input field (a phasor of length ½). Push-pull drive turns the arms equally and oppositely (+Δφ/2, −Δφ/2), so their sum (accent) always lies on the real axis: amplitude without phase wobble (no chirp), passing through zero and changing sign. Tick the box to drive one arm only: the sum then swings off the axis. Model: mzmArms.

03

The Transfer Curve and Three Bias Points

The power transfer curve is a raised cosine. As with a transistor, you choose a DC operating point (the bias, set by a slow phase shifter inside the arms) and the data swings either side of it. Three bias points matter. textbook

Left: power (solid) and field (dashed) against the arm phase difference; the shaded band is the drive swing about the current bias, its ends the '1' and '0' levels. Right: the two levels on the complex field plane, the circle being the maximum field. Step through peak, quadrature and null; drag the slider to change the swing. Model: biasPoint.

BiasΔφField '1'Field '0'Field stepPower '1'Power '0'Power step
peak00.9410.9410.0000.8850.8850.000
quadratureπ/20.9050.4260.4790.8190.1810.637
nullπ0.339-0.3390.6770.1150.1150.000

Source: results.md, section “Drive ±0.22 Vπ”

Peak (Δφ = 0)

  • Full power; the curve is flat, so the first-order response is zero.
  • Rarely used for data.

Quadrature (π/2)

  • Power responds linearly and most steeply; both field levels are positive.
  • Ordinary NRZ and PAM4 datacom optics (intensity modulation, direct detection). RF analogue: AM with a carrier.

Null (π)

  • The field passes through zero linearly and changes sign; '0' and '1' have equal power.
  • Coherent formats (BPSK, QPSK, QAM). RF analogue: double-sideband suppressed carrier.

At ±0.22 Vπ the field step is 0.677 at null against 0.479 at quadrature (of the maximum field): the field is steepest at null, the power at quadrature.

04

“Quadrature” Has Two Meanings

Warning

In optics, “quadrature” names two different things. Ask which one is meant.

1 · quadrature bias half power Δφ = 90°180°360° P arms 90° apart (MZM) 2 · I/Q quadrature I (cos)Q (sin) 90° two carriers 90° apart

Left: a modulator biased at quadrature, the half-power point, its two arms 90° apart (slide 03). Right: I/Q quadrature, two carrier components 90° apart in phase, as in an IQ modulator (slide 05) or a 90° optical hybrid (slide 08).

05

The Textbook Coherent Transmitter

Every coherent long-haul transceiver writes its data with an IQ modulator: two MZMs, each biased at null so it is a signed, carrier-free modulator, combined 90° apart so the output is one complex field E = I + jQ. textbook (Seimetz, High-Order Modulation for Optical Fiber Transmission, 2009; Kikuchi, J. Lightwave Technol. 34, 2016)

laser MZM, nullI data ± MZM, nullQ data ± +90° I + jQ child MZMs at null; parent 90° apart |E| LO axis ReIm QPSK: 2 bits per symbol

Left: the IQ modulator. Right: its QPSK constellation, one point per symbol (real part across, imaginary part up); noise spreads each point into a cloud, and the receiver picks the nearest point. A photodiode sees only the squared distance from the origin (the dashed circle: all four QPSK points look the same). A homodyne receiver sees the projection onto its LO axis (dashed amber).

06

Why Quadrature Bias Suits Unsigned Bits

At quadrature each lane's field is E0 + d·x, with x a bit (0 or 1): a constant carrier E0 (the '0' level) plus a data step d. The optical Fourier transform is linear, and the DFT of a constant lands only in bin k = 0. derived

DFT([E0, E0, E0, E0] + d·bits) = [4E0, 0, 0, 0] + d·DFT(bits)

Top: the four lane fields (√µW), carrier part (grey) and data part (teal). Bottom: the four outputs Y = DFT(x)/2 (the transform is unitary, so it scales by ½), real parts teal and imaginary parts amber, with the carrier's share hatched. The carrier adds 2E0 = 5.62 √µW to output 1 (130.0 µA of detector current) and nothing to outputs 2–4. Model: chainModel with the illustrative parameters of slide 09.

What follows from the maths derived

  • The carrier only touches output 1, as a fixed offset that calibration removes. Outputs 2–4 see exactly d × DFT(bits) (halved by the unitary transform).
  • Null bias would compute the same thing. Signed inputs ±1 are 2x − 1: again a constant (which lands in output 1) plus a scaled copy of the bits.
  • Null's advantages are real but modest here: a larger field step per volt (slide 03) and no offset to calibrate out.

Why quadrature is still a good choice inference

  • At quadrature '0' and '1' have different powers, so slow monitor photodiodes and intensity-based calibration steps can see the data. At null they cannot.
  • It is the easiest bias to find and hold (slide 07).
  • Datacom drivers and process-design-kit modulators are made and characterised for it.

The patent's word is quadrature (slide 04) patent; the reasons in the right-hand box are this deck's, not the patent's.

07

Holding the Bias Point

Bias points drift with temperature and ageing, so a slow loop holds them. What the loop can measure depends on where it is holding. textbook

Top left: the transfer curve, the bias (dot) and the dither's excursion either side. Top right: the monitor power over two dither periods (the dither is 0.1 rad, exaggerated in the drawing). Bottom: the three error signals against bias phase, from a numerical lock-in (dither, checked against its Bessel-function form in the tests). The 1st harmonic is drawn ×10 and the 2nd ×200; dots are the recorded values in results.md.

Holding quadrature

  • Power changes to first order with drift. The error is simply average monitor power (normalised to the peak, or ratioed against an input tap) − ½, fed to an integrator: a DC servo. The integrator's sign picks which of the two quadrature points (π/2 or 3π/2, opposite slopes) it holds.

Holding null (or peak)

  • The power is at an extremum: drift either way raises it, so the level alone cannot say which way to move.
  • Add a small dither tone and detect synchronously (lock-in): the 1st-harmonic response is the slope, zero exactly at null, with a sign. The RF equivalent: nulling an IQ mixer's LO leakage.
Bias phaseAvg power − ½1st harmonic2nd harmonic
0π+0.4988+0.0000+0.00125
0.25π+0.3527-0.0353+0.00088
0.5π+0.0000-0.0499+0.00000
0.75π-0.3527-0.0353-0.00088
1π-0.4988+0.0000-0.00125
1.25π-0.3527+0.0353-0.00088
1.5π+0.0000+0.0499+0.00000
1.75π+0.3527+0.0353+0.00088
2π+0.4988+0.0000+0.00125

Source: results.md, section “3. Holding the bias”

08

Direct and Coherent Detection

Direct detection is one photodiode measuring power: enough for intensity data, blind to sign and phase. Coherent detection mixes the signal Es with a local oscillator (LO) of the same frequency in a 2×2 coupler and subtracts the two photodiode currents (a balanced pair): textbook

i = i1 − i2 = 2·R·Re(Es·ELO*) = 2·R·√(Ps·PLO)·cos Δφ

Left: output 2's nine possible fields (õW, slide 10), the dashed circle being what direct detection can tell apart (only |E|). The LO phase sets the axis (amber); each point's projection on it is what the balanced pair reports. Right: the projected levels as currents (slide 09's scale), and for the highlighted point the two photodiodes' currents: each carries the large common term R(Ps+PLO)/2, which the subtraction removes. Model: balancedPair, chainModel.

What the receiver gets

  • Sign: the output is linear in the field.
  • Gain: the signal grows as √PLO, lifting a weak signal above the amplifier's noise (slide 14).
  • A chosen projection: Δφ = 0 reads the real part, 90° the imaginary part, as in a zero-IF radio. A 90° hybrid gives both at once.
  • Balance cancels the LO's power and most of its intensity noise (to the pair's common-mode rejection).

Kinds of coherent receiver

  • Homodyne: LO at the signal's frequency, phase-locked.
  • Heterodyne: an offset, so an intermediate frequency.
  • Intradyne: nearly the same frequency, phase tracked in DSP (modern telecom).
  • Self-homodyne: the LO split from the same laser, so its phase noise cancels except over any path-length mismatch.

The module: one of the laser's seven channels becomes the LO, through a slow MZI “to control both phase and intensity”, split four ways with a phase shifter each; each copy is mixed with one transform output, and “All coherent homodyne detection techniques used in the PIC use balanced PDs.” paper Self-homodyne, in the terms above. derived

09

Constellations Through the Chain

One input vector, followed from the FPGA's transmitter to the decoded answer, with the signal drawn as a constellation at every stage. Choose any of the 16 inputs; tick the box to see the illustrative uncalibrated phases. The stages follow the paper and patents; the numbers are illustrative (parameters in section 1 of results.md). illustrative

Top: where the signal is. Below: its constellation at that stage. Faint points: all 16 inputs; bright: the chosen one; dashed: the axis each detector's LO projects onto; dotted (from stage 5): decision thresholds. Model: chainModel, pam4Symbols, decode, the port of link_hw.py.

The worked example, input [1, 0, 1, 1]:

StageWhat the signal isWorked example
0 · FPGA transmitterFour binary NRZ lanes at 14 GBaudbits 1, 0, 1, 1
1 · DriverLinear amplification to ±1.50 V (illustrative Vπ 6.8 V, so ±0.22 Vπ)+1.50 V, −1.50 V, +1.50 V, +1.50 V
2 · MZM at quadratureField 0.905 ('1') or 0.426 ('0') of the maximum; power 82% or 18%lane maximum 43.6 µW; fields 5.97, 2.81, 5.97, 5.97 √µW; carrier E₀ = 2.81, step d = 3.16
3 · Per-lane phase shiftersSet by calibration so the lanes arrive in phaseuncalibrated: lanes turned by 0°, 25°, -15°, 10° (illustrative)
4 · Optical Fourier transformY = DFT(x) / 2, x = E₀ + d·bitsDFT(bits) = [3, j, 1, −j]; Y = [10.36, 1.58j, 1.58, −1.58j] √µW
5 · Balanced homodynei = 2·R·E_LO × projection; E_LO = 17.78 √µW, so 23.1 µA per √µWcurrents 239.6, 0.0, 36.6, -36.6 µA
6 · TIA and offset removal1,000 Ω; output 1's carrier offset 130.0 µA removed239.6, 0.0, 36.6, -36.6 mV; output 1 after offset 109.7 mV; levels 3, 0, 1, -1
7 · PAM4 into the FPGAOutputs 1 and 3 clip their top levelsymbols 3, 1, 3, 0
8 · FPGA decodeRebuild X, inverse DFTX = [3, j, 1, −j]; bits [1, 0, 1, 1]

Source: results.md, section “4. Constellations through the chain”

10

The DFT Alphabet

The transform computes a 4-point DFT, Xk = Σn xn·(−j)kn, whose only weights are 1, −j, −1 and j. With bits for inputs, the outputs take a small, fixed set of values: the module's output alphabet. derived

Step through all 16 inputs (dft4Int). Each panel is one output on the complex plane; points already visited stay. Outputs 1 and 3 fill five levels on the real axis; outputs 2 and 4 fill 3×3 grids that are mirror images (complex conjugates) of each other for every input.

OutputValues takenDistinct
1real, 0, 1, 2, 3, 45
2complex, −1 − j, −1, −1 + j, −j, 0, j, 1 − j, 1, 1 + j9
3real, −2, −1, 0, 1, 25
4complex, −1 − j, −1, −1 + j, −j, 0, j, 1 − j, 1, 1 + j9

Source: results.md, section “5. The DFT alphabet”

11

Calibration: Rotation and Distortion

Every optical path has its own phase, set by fabrication and temperature. Phase errors before the transform and after it do different damage, which is why calibration fixes them in a fixed order. Toggle either kind and step through the calibration.

Left: output 2's constellation for all 16 inputs (dots) against the calibrated grid (rings). An output error rotates it rigidly; an input error distorts it (the transform computes with the wrong weights). Right: the levels each detector reads, in level steps, with decision thresholds (dotted); a wrong decision is drawn as a cross in the warning colour. Phase errors 0°/25°/−15°/10° (input) and 20°/−30°/15°/35° (output) are illustrative. Model: detectedLevels, decide.

Phase errors presentWrong decisions (of 64)Largest error (steps)Passes
both (uncalibrated)321.00no
input path only80.71no
output/LO path only80.75no
none (calibrated)00.00yes

Source: results.md, section “7. Calibration”

1 · MZMsquadrature 2 · ref.phase 3 · LOlevel: max 4 · LOphase 0→π 5 · inputphase 0→2π 6 · all 16tweak reference first, then the receivers (4), then the transmitters (5) pass: every output within ½ level step 1 · MZMs to quadrature 2 · reference phase 3 · LO level to max 4 · LO phases 0→π 5 · input phases 0→2π 6 · all 16, small tweaks pass: within ½ level step

patent The start-up calibration of WO2025168828A1 (a patent cited by the paper), with the stream paused and known input vectors applied: set the modulators to quadrature; set the system's reference phase with one input switched on; set the LO amplitude to maximum; sweep each LO phase “from 0 to pi radian” until each output matches a DFT lookup table; sweep each input's phase “from 0 to 2pi radian” until all outputs match the truth table; then cycle all 16 vectors with small tweaks.

12

From PAM5 and PAM3 to PAM4

“The transmitted data to the module is restricted to binary (NRZ) levels. This is to compress the photonic computed result to PAM4”, and the results return on the QSFP56 port's receive lanes. paper But outputs 1 and 3 have five levels (slide 10), and PAM4 has four.

output 1 (0…4)output 3 (−2…2) outputs 2 and 4: levels −1, 0, 1 → symbols 0, 1, 2 (three of the four) output 1 (0…4)output 3 (−2…2) outputs 2, 4: −1, 0, 1 → 0, 1, 2

Saturation packing, as drawn here: the top level of outputs 1 and 3 is clipped onto the one below it (warning colour). inference This deck's mapping is illustrative; the patents' own level coding differs (for example, raw levels offset per channel so one receiver design serves all four).

What the patent describes patent

  • Two packings that keep the result recoverable (WO2025168827A1): carry add (detect the fifth level on outputs 1 and 3, subtract it, and add two levels to output 2's PAM3) and saturation (clip the fifth level onto the fourth and recover it from the other channels).
  • Saturation “can be done on the receiver itself by reducing the dynamic range of the receiver”: a receiver run into compression does the job.

Why the FPGA can undo the clip inference

  • X0 − X2 = 2(x1 + x3) is even, so outputs 1 and 3 have the same parity: a clipped 3 on output 1 is told from a true 3 by output 3's level.
  • In two of the 16 cases (1110 and 1011 in the table, column “Candidates after parity”) parity leaves two candidates; the impossible one is ruled out because a sum of 4 forces every other output to 0.
  • Carry-add needs logic that sees several channels before the FPGA, which the module does not report; saturation needs none. So saturation looks the likelier route here, and the FPGA's own PAM4 receiver doubles as the module's ADC.
InputX (DFT of the bits)PAM4 symbolsDecoded
00000, 0, 0, 001210000
10001, 1, 1, 112311000
01001, −j, −1, j11120100
11002, 1 − j, 0, 1 + j22221100
00101, −1, 1, −110310010
10102, 0, 2, 021311010
01102, −1 − j, 0, −1 + j20220110
11103, −j, 1, j31321110
00011, j, −1, −j11100001
10012, 1 + j, 0, 1 − j22201001
01012, 0, −2, 021010101
11013, 1, −1, 132111101
00112, −1 + j, 0, −1 − j20200011
10113, j, 1, −j31301011
01113, −1, −1, −130110111
11114, 0, 0, 031211111

Source: results.md, section “6. Packing into PAM4”

16 distinct symbol patterns for 16 inputs; every input decodes back to itself. Parity alone settles every clipped case but 2; there the inverse DFT rules out the impossible candidate.

13

The Receiver: What a TIA Does

“The PDs in the PIC are packaged with Single Layer Capacitors (SLCs) and bonded with a TIA die.” paper A transimpedance amplifier (TIA) turns the balanced pair's difference current into a voltage. The SLCs give the photodiode bias an AC ground right at the diode, and a bare TIA die bonded beside the chip keeps the input capacitance and the bond-wire inductance small. inference

+bias−bias PD₁PD₂ i₁ − i₂ −A R_F VGA v_out DC-offset loop

Left: a shunt-feedback TIA on a series balanced pair, with a variable-gain stage and a slow DC-offset loop (a typical linear-TIA architecture; the module's internal blocks are not reported). Right: the transimpedance limit RT ≤ A·fA/(2π·CT·f3dB²) (Säckinger, 2017) for three input capacitances, with an illustrative 1 THz gain-bandwidth; dotted at 0.6 × 14 and 0.6 × 56 GBaud. Model: tiaLimit.

C_TR_T max at 8.4 GHz (14 GBaud)R_T max at 33.6 GHz (56 GBaud)Ratio
80 fF28,195 Ω1,762 Ω16×
150 fF15,037 Ω940 Ω16×
300 fF7,519 Ω470 Ω16×

Source: results.md, section “9. The transimpedance limit”

A five-level signal through a linear TIA (levels kept) and a limiting TIA (levels crushed onto its rails). Illustrative transfer curves.

Linear, not limiting textbook

  • A limiting TIA saturates on purpose: fine for NRZ, fatal for computed multi-level results. A linear TIA keeps the levels; its compression shifts the outer ones, a calibration term until it crosses a threshold.
  • Doubling the bandwidth costs four times the gain; doubling the capacitance costs two.

Datacom TIAs and computed levels inference

  • Automatic gain control holds the output swing constant, which suits datacom (the information is in relative levels) but rescales computed ones, and reacts to the data statistics. Fixed (manual) gain, or re-calibrating thresholds when the gain changes, is safer.
  • A balanced pair's current averages near zero. A datacom TIA built for one photodiode's one-way current may read its signal strength as zero, sit at maximum gain, or let its DC-offset loop remove output 1's data-dependent mean.
  • Computed results cannot be scrambled (that would change the answer), so long runs and a high-pass corner cause baseline wander.
14

The Noise Budget

Is there enough signal-to-noise? Three noise currents compete with the balanced pair's signal: the TIA's own noise (flat), shot noise (grows as √PLO, like the signal) and the LO's intensity noise left after imperfect balance (grows as PLO). A decision fails when noise crosses half a level step, so the figure of merit is Q = (step/2)/σ; Q ≈ 4.9 gives about 10−6 errors per decision. textbook

Left: signal (peak, output 3's full swing) and rms noise currents against LO power per detector pair. Right: Q per level step for outputs 1 and 3 (output 1 carries more power, so more shot noise), with the requirement Q = 4.9 (dotted) and the illustrative −5 dBm operating point (dot). Responsivity 0.65 A/W from a foundry Ge photodiode (Hu et al., Photonics Research 11, 2023); TIA noise 10 pA/√Hz, RIN, CMRR and signal power are illustrative; 7 GHz noise bandwidth (Nyquist at 14 GBaud). Model: homodyneTerms, qPerStep.

TermCurrent
Peak signal (output 3's full swing, two steps)73.10 µA
TIA noise (rms)0.84 µA
Shot noise (rms)0.69 µA
LO RIN after CMRR (rms)0.05 µA
Total noise (rms)1.09 µA

Source: results.md, section “8. Noise budget”

OutputQ per stepMargin over Q = 4.9Range to handle
115.610.1 dB130 to 276 µA (7.6 steps)
316.810.7 dB-73 to 73 µA (±2 steps)

Source: results.md, section “Margins”

Noise bandwidthTIA noise (rms)Total noise (rms)Q, output 3Margin over Q = 4.9
7 GHz0.84 µA1.09 µA16.810.7 dB
20 GHz1.41 µA1.84 µA10.06.2 dB
35 GHz1.87 µA2.43 µA7.53.7 dB

Source: results.md, section “Noise bandwidth”

15

Skew: Four Lanes Summed Before Any Decision

In an ordinary four-lane link each lane has its own clock and data recovery, and lanes are deskewed digitally after decisions. Here the four lanes are added optically before any decision: near its edges a late lane still carries its previous bit, so the sum is partly the wrong answer and the eye closes. derived

Left: the summed signal (output 1 of the transform, unit weights) over two unit intervals, 160 traces, four PRBS15 lanes through a Gaussian channel, lane 1 late by the step's skew. Right: the worst inner-eye opening (in level steps, at the best sampling time) against skew, recorded in results.md; the dot is the live model. Model: filtered, eyeOpening.

Skew (UI)ps at 14 GBaudps at 56 GBaudOpening (BW 0.75 × baud)Opening (BW 0.5 × baud)
00.00.00.9780.728
0.06254.51.10.9750.715
0.1258.92.20.9640.685
0.187513.43.30.9460.639
0.2517.94.50.9170.575
0.312522.35.60.8740.493
0.37526.86.70.8130.396
0.437531.37.80.7290.282
0.535.78.90.6180.150

Source: results.md, section “10. Skew”

Source of skewRule of thumbFix
FPGA transmitter lanesLanes may start with arbitrary phase unless they share a clock and are phase-alignedCommon reference clock, transmit phase alignment, per-lane fine delay
PCB traces≈ 6–7 ps per mm of stripline (√εr ≈ 1.9–2.0 over c)Length-match the pairs to well under 1 mm
On-chip optical paths≈ 13 ps per mm of mismatch (group index ≈ 4 in a silicon wire)Path-matched layout: the paper's “phase balanced PIC” paper
Driver channels, bond wiresA few psEqual bond lengths; calibrate out

At 14 GBaud a tenth of a unit interval is 7 ps; at 56 GBaud, which the module's drivers and TIAs support paper, it is 1.8 ps, which makes skew a first-order layout constraint for a faster chip. derived

16

What a Simulator Needs From All This

Each hardware effect on the previous slides becomes a term in a system model. A simulator of a link like this one is a chain of small, testable models, each with parameters that can be measured on the bench.

TX lanesskew, ISI MZMbias, Vπ phase indrift, cal. DFT/2loss, xtalk LO, PDsP_LO, CMRR TIA, PAM4noise, clip calibration loop: slow, quasi-static validate each block on the bench, then the chain against measured error rates TX lanes: skew, ISI MZM: bias, Vπ phase in: drift, cal. DFT/2: loss, xtalk LO, PDs: P_LO, CMRR TIA, PAM4: noise, clip calibration loop: blocks 3 to 5

The chain as a simulator sees it: one block per physical stage, each with the parameters that move its output.

Hardware parameterModel termSlide
Drive swing, VπThe two field levels f0, f1 = cos((Δφ ± πV/Vπ)/2): the carrier E0 and step d02, 03
Bias driftA shift of Δφ: changes E0 and d, so output 1's offset and every step07
Input-path phasesA complex weight per lane before the transform: distorts the constellation11
Output and LO phasesA rotation of each output before projection: mixes real and imaginary parts08, 11
LO power, responsivitySignal gain 2R√PLO; shot noise08, 14
Photodiode imbalance, CMRRResidual DC and LO intensity noise14
TIA noise density and bandwidthAdditive Gaussian noise, σ growing as √B (and faster from the amplifier's voltage noise)13, 14
TIA gain mode, compression, DC-offset cornerLevel scaling, outer-level compression, baseline wander13
Lane skew, channel bandwidthInter-symbol interference in the optical sum15
Saturation and codingThe map from levels to PAM4 symbols and back12
Thermal drift, calibration intervalSlow phase random walk, reset by the calibration state machine11

Every model on these slides is in analysis/link_hw/link_hw.py, first-order and labelled; a real simulator would add each block's measured transfer function. The system-level questions a link like this raises are the subject of the Compute in Transit series.

17

What to Take Away

bits → fieldstwo + levels DFT → signedPAM5, 3×3 grids LO → project3 Re + 1 Im clip → PAM4FPGA decodes calibration keeps every level within half a step

The deck in one line.

Sources

The module: Kundu et al., “Programmable Compute-in-Transit using Integrated Photonics”, arXiv:2608.21536. Patents cited by the paper: WO2025168828A1 (calibration and stabilisation), WO2025168827A1 (dense data packing to PAM4), GB2616426A (optical encoders, balanced homodyne detection), EP4677399A1 (the optical Fourier transform device). Textbook and literature: Kikuchi 2016 and Seimetz 2009 (coherent detection and modulation), Säckinger 2017 (TIAs), Hu et al. 2023 (photodiode responsivity), Félix Rosa et al. 2017 (silicon MZM VπL), Harris et al. 2014 (thermo-optic phase shifters). Numbers: analysis/link_hw/results.md.

Where the module fits: FOptInf 01, the case study and its slab lens; what it could compute on in LLM training and inference traffic: Compute in Transit 01.