History of Arm & the Architecture

• Many Cortex-M design choices only make sense once you understand what Arm was in 1985, 1994, and 2004.
• The Thumb-only M-profile, the fixed memory map, the NVIC priority model — all are reactions to specific historical pain points.
• The IP licensing model Arm pioneered is why the same core design ships in 220+ different MCU SKUs today.
• Interview panels love "why is it like this?" questions — a quick history of the architecture is often the cleanest answer.

• Acorn Computers founded in Cambridge (UK), 1978 by Chris Curry, Hermann Hauser, and Andy Hopper.
• Built the Acorn System 1 (6502-based) and then won the BBC Micro contract in 1981 — 1.5 M units sold, one per UK classroom.
• Acorn's next-gen PC needed a faster CPU. They evaluated the Intel 80286 (rejected — poor interrupt handling), Motorola 68000 (too slow, too complex), and National Semi NS32016 (too expensive).
• After reading papers on RISC from Berkeley (Patterson, RISC-I 1981) and Stanford (MIPS, 1983), Sophie Wilson and Steve Furber proposed designing Acorn's own RISC processor.

• Team of ~6 people, led by Sophie Wilson (ISA) and Steve Furber (microarchitecture).
• VLSI Technology fabbed it on a 3 µm process. 25,000 transistors — smaller than a 6502.
• 32-bit architecture, 32-bit registers, 26-bit program counter packed into R15 with status flags.
• 3-stage pipeline: Fetch — Decode — Execute. Every instruction conditional. Barrel shifter in the ALU path "for free".
• Famous story: the test chip drew so little power (a few hundred mW) that when the designers probed the V_dd pin they found it disconnected — the chip was running on leakage from the I/O pads.

ARM = Acorn RISC Machine — renamed to Advanced RISC Machines in 1990.

ARM2 (1986)

• First Arm to ship in a commercial product: the Acorn Archimedes A305 (June 1987) — the world's first RISC-based desktop computer.
• 8 MHz, ~30,000 transistors, 4 MIPS — out-ran a 16 MHz 80386 on integer code.
• No cache, no MMU, no FPU. Ran the Arthur/RISC OS at desktop-responsive speed.

ARM3 (1989)

• Added a 4 KB unified cache on-die — first Arm to have any cache.
• 25 MHz, ~310,000 transistors.
• Last Acorn-designed Arm before the Apple spin-out.

• Apple was developing the Newton MessagePad — needed a low-power 32-bit CPU.
• The Newton team (Larry Tesler) evaluated Arm and loved it, but Acorn was a flaky British PC maker with no long-term prospects.
• November 1990: Apple, Acorn, and VLSI Technology jointly founded Advanced RISC Machines Ltd — 12 engineers, one conference room in Cambridge.
• The new Arm was a pure IP licensing company: no fab, no products, just designs sold to whoever wanted to build silicon.
• Apple invested £1.5M for 43% of the new company; VLSI 43%; Acorn 15%.

ARM6 (1992) → ARM7 (1994)

• ARM6 was used in the Newton MessagePad.
• ARM7 added a 3-stage pipeline (deeper fetch), higher clock.
• Crucially, Arm introduced Thumb — a 16-bit compressed instruction set — in 1994.

ARM7TDMI (1994)

• Thumb, Debug, Multiplier, ICE-RT.
• Nokia picked it for the 6110 (1998); Texas Instruments put it at the heart of the OMAP baseband.
• By 2000, ARM7TDMI was in hundreds of millions of mobile phones — the single most-shipped 32-bit core of the 20th century.

• By the early 2000s, a single Arm ISA (ARM7/ARM9/ARM11) had to serve phones, servers, MCUs, and automotive.
• Each market pulled in a different direction:
  • Phones/servers — caches, MMU, virtualisation.
  • Automotive/industrial — deterministic timing, lockstep CPUs.
  • MCUs — small die, fast IRQ, no MMU, low power.
• Arm's answer: split Armv7 into three profiles.

Thumb-1 (1994)

• 16-bit encoding of a subset of A32 instructions.
• Code density ~30% better than A32; performance ~70%.
• Phones used Thumb to save ROM mask costs.

Thumb-2 (2003)

• Added 32-bit encodings for instructions that wouldn't fit in 16 bits.
• A single compiler output could reach all A32 functionality while still averaging ~16-bit code size.
• Thumb-2 could replace A32 entirely.

M-profile decision (2004)

• Strip out A32 state altogether. No mode switch. No CPSR.T bit toggling.
• All exception handlers and interrupt vectors are Thumb.
• Benefits:
  • Simpler pipeline (one decoder).
  • Smaller die area.
  • Uniformly dense code — crucial when flash is 32–64 KB.
  • Deterministic code size for ROM vendors.

• Arm does not fab chips. It licenses synthesisable RTL (the "core IP") plus tool flows, compilers, and reference designs.
• Typical licence structure:
  • Per-design licence — paid once per SoC tape-out.
  • Royalty — a few pence per chip, for the life of the product.
• Arm Flexible Access (2019) — a subscription that bundles most Cortex-M cores + tools for start-ups & small teams. Lowered the barrier to a first Cortex-M SoC to ~€75k / year.
• Cortex-M0 DesignStart (2017) — free-to-license M0 + interrupt controller for academic / evaluation use.
• 220+ companies license Cortex-M today.

From ARM1 (1985)

• Load/store architecture — compute only between registers.
• 16 general-purpose registers — R0–R15, same layout 40 years later.
• R13=SP, R14=LR, R15=PC convention unchanged.
• Pipelined design with in-order execution.

From ARM7TDMI (1994)

• Thumb — compact 16-bit encoding.
• Debug — architected debug interface (CoreSight evolved from this).
• ICE-RT — halting debug concept.

From ARMv5E (1999)

• DSP extensions — saturating arithmetic, double-MAC (now in Cortex-M4+).

From Armv7-M (2004)

• NVIC in the core.
• Thumb-2 full ISA.
• Profile split — M-profile became its own thing.

From Armv8-M (2016)

• TrustZone, stack-limit registers, SAU/IDAU.

From Armv8.1-M (2019)

• Helium (MVE), low-overhead loops, PACBTI.

• "Why Thumb-only?" → code density + pipeline simplicity; the Archimedes-to-Newton lineage cared about ROM cost first, silicon area second.
• "Why is the NVIC architectural?" → because Arm's 2004 profile split made the interrupt controller part of the CPU contract; portability of driver code.
• "Why is the priority field 8 bits but only top N used?" → forward-compatibility: a driver compiled for a 4-bit impl works on an 8-bit impl without changes.
• "Why did v8-M bring TrustZone to MCUs?" → PSA & IoT security economics (2014–2016) required root-of-trust isolation without a second chip.

• "Why did M7 bring caches but M3/M4 didn't?" → flash wait-states became dominant at 300+ MHz; caches hide them. At < 100 MHz, single-cycle flash makes caches unnecessary.
• "What's the difference between Helium and NEON?" → Helium is 128-bit beat-wise SIMD designed for MCU area; NEON is a full 128-bit SIMD block on A-profile. Different instruction set, different micro-architecture.
• "Is Cortex-M relevant now?" → M-profile accounts for the majority of Arm units shipped. Every Wi-Fi dongle, smartwatch companion, car door-lock sensor, washing-machine controller ships one.