Inside Pascal — The First HBM and NVLink GPU

Topics We'll Cover

A low-level tour of NVIDIA's Pascal generation — the die plan, the SM, arithmetic units, process, voltage and clocks, memory, NVLink, and the things Pascal introduced to the rest of the GPU industry.

• Pascal at a Glance
• GP100 Die — Block Diagram
• The Pascal SM (GP100 Variant)
• Arithmetic Units & FP16x2
• Process — TSMC 16FF+ & Samsung 14LPP
• Voltage, Power, Package
• Clocks & Speeds
• Memory — HBM2 First Time, GDDR5X Second
• NVLink 1.0 — The Original
• PCIe 3.0, Display, NVENC/NVDEC
• Pascal's Innovations
• Interactive: Pascal SKU Picker

Pascal at a Glance

Pascal launched in 2016 as the first 16 nm NVIDIA architecture, and the first to ship HBM2 and NVLink. Two distinct die families: GP100 for HPC/AI on TSMC 16FF+ with HBM2, and GP102/104/106/107/108 for graphics on the same node with GDDR5/5X.

GP100 Die — Block Diagram

GP100 is organised as a hierarchy of clusters. The top-level chip-wide units are the L2 cache slices, the memory controllers, and the host interface; everything else fans out from a small number of GPCs (Graphics Processing Clusters).

Each GPC contains a raster engine, 5 TPCs, and per-GPC fixed-function graphics blocks. Each TPC is two SMs sharing texture units. Total: 60 SMs on a 610 mm² die.

The Pascal SM (GP100 Variant)

The GP100 SM is split into two partitions, each with its own warp scheduler. Total per SM:

GP10x graphics SMs differ: 128 FP32 cores per SM (4 partitions of 32) but only 4 FP64 cores per SM (1:32 rate) and no FP16x2 dual-issue. Larger 96 KB shared memory is statically partitioned with a 48 KB L1.

Arithmetic Units & FP16x2

Pascal predates tensor cores. Every matmul runs on the FP32 SIMT lanes — no fused multiply-accumulate at higher density. The architecture's headline arithmetic feature was FP16x2: pack two FP16 values into one 32-bit register and execute one packed instruction per cycle, doubling the FLOP rate over scalar FP16. This was the first hardware support for half-precision deep learning at full throughput.

Process — TSMC 16FF+ & Samsung 14LPP

Pascal was NVIDIA's first FinFET node, an enormous density jump over Maxwell's planar 28 nm. GP100, GP104, GP106 on TSMC 16FF+; GP107, GP108 on Samsung 14LPP (lower-cost, lower-leakage variant). 16FF+ delivered roughly 2× transistor density and 30% lower switching energy versus 28HPM Maxwell.

Voltage, Power, Package

Pascal's core voltage runs 0.80–1.06 V depending on boost state, with a per-die voltage curve baked into the GPU's bootstrap. Power delivery on P100 SXM uses a 16-phase digital VRM at 700 A peak; reference GTX 1080 Ti boards use 7+2 phase designs at ~250 A.

P100 was the first NVIDIA part to use a 2.5D silicon-interposer package — GPU die plus four HBM2 stacks bonded onto a passive silicon interposer mounted on an organic substrate. CoWoS-S was new at TSMC; yields were challenging through 2016.

Clocks & Speeds

Pascal introduced GPU Boost 3.0 — each voltage point on the V/F curve is independently programmable, allowing per-state overclocking. Modern nvidia-smi -q -d CLOCK still reports the same V/F state machine that Pascal first exposed.

Memory — HBM2 First Time, GDDR5X Second

Pascal shipped the industry's first HBM2 product. P100 connects to 4 stacks of 4-Hi HBM2 over a 4096-bit bus; each stack is 4 GB at launch. GP10x graphics dies use GDDR5 or the new GDDR5X (Micron's quad-data-rate variant, still NRZ signalling, doubling the per-pin rate at the same clock as GDDR5).

NVLink 1.0 — The Original

NVLink 1.0 is Pascal's other industry-first. Each link is 8 differential pairs × 20 Gbps NRZ = 20 GB/s/dir = 40 GB/s/link bidirectional. P100 has 4 NVLinks for an aggregate 80 GB/s/dir, 160 GB/s bidirectional — ~5× PCIe 3.0 x16. Topology: in DGX-1, eight P100s wired in a hybrid cube-mesh; no NVSwitch yet, so with 4 links per GPU only 16 of the 28 GPU pairs are directly linked; the other 12 take 2 hops.

PCIe 3.0, Display, NVENC/NVDEC

Pascal's Innovations — What It Put on the Map

• HBM2 in production. First commercial NVIDIA part with 2.5D HBM packaging (P100, June 2016). The interposer process and stack supply chain that Hopper and Blackwell still use trace back here.
• NVLink 1.0. The first GPU-to-GPU coherent-ish high-speed link — the foundation every later NVL generation builds on.
• FP16x2 packed math. First widely-used hardware acceleration for half-precision deep learning. Set the precedent for tensor-core formats.
• Unified memory page faulting. Pascal added hardware support for handling page faults on the GPU, allowing CUDA managed memory to oversubscribe the GPU's VRAM — pages migrate on demand.
• GPU Boost 3.0. Per-V/F-state overclocking; the framework still in nvidia-smi today.
• 16 nm FinFET. First NVIDIA FinFET node; doubled density and cut leakage versus Maxwell 28 nm.
• SXM2 mezzanine. Standardised the proprietary mezzanine connector that became HGX A100 / H100 / B200's basis.

Interactive: Pascal SKU Picker