DynamIQ Shared Unit

• big.LITTLE (2011-17) locked you into two fixed clusters with CCI-400 coherence in between. Every cluster had its own L2. Thread migration was expensive.
• Phones wanted 3-4 performance tiers: X-core, mid-A-core, LITTLE. Two clusters can't express that.
• DynamIQ (2017), introduced with Cortex-A75 + A55, is a single-cluster multi-core unit that supports up to 8 heterogeneous cores.
• Integrated Snoop Control Unit (SCU) + optional L3 cache + per-core async bridges — no external CCI needed.
• Enables the modern 1 + 3 + 4 layout (1 X + 3 A + 4 LITTLE) inside a single cluster.

• Up to 14 heterogeneous cores (X / A-mid / A-LITTLE) share the same L2 snoop + L3 cluster.
• The SCU tracks which cores hold which lines — targeted snoops, not broadcast.
• L3 is sliced, typically 4 slices × 4-8 MB = 16-32 MB total.
• CHI egress to the SoC — NIC-700 or CMN mesh in larger systems.
• Per-core async interfaces let each core run at its own clock + voltage.

• L3 is distributed across 4-8 slices. Slice count is design-time configurable.
• Each slice is independent — own tag RAM, own arbiter. Misses go to the SCU for lookup.
• Address → slice mapping is a hash (usually XOR of address bits). Spreads load evenly across slices at cache-line granularity.
• L3 is typically mostly-inclusive of L2 — lines in L2 have an entry in L3 for coherence tracking, but clean unmodified data is not duplicated.
• Per-slice power domain — idle slice can be gated off (DSU-110+). DSU-120 allows up to 75% of L3 to be gated in low-power idle.

• The Snoop Filter tracks which cores have copies of which cache lines in their L1 / L2. Sized roughly for ~1.5× the sum of L2s.
• When a core misses in its own L2, the SCU consults the filter:
  • If another core holds the line Unique, request is satisfied by cache-to-cache transfer (no L3 or DRAM).
  • If held Shared, the requester gets a fresh copy from L3.
• Makes Dekker-lock style patterns efficient — two cores on the same cluster can ping-pong a cache line at L2 speed.
• Also where LSE atomics land — single-cluster atomics run locally in the SCU with no mesh traversal.

// Producer/consumer across DSU cores

// Core 0 (X-core, producer)
str  x1, [data_ptr]         // write data
stlr w2, [flag]             // release-store

// Core 1 (A-mid, consumer)
1:  ldar w3, [flag]         // acquire-load
    cbz  w3, 1b
ldr  x4, [data_ptr]         // safe read

// Coherence flow inside DSU:
//   Core 0 owns line Unique in its L2
//   STLR broadcasts invalidate → SCU filter
//   Core 1 LDAR misses → SCU says Core 0 has it
//   → cache-to-cache transfer (~20 cycles)
//   No L3 or DRAM needed

• Each core has its own asynchronous clock bridge and potentially its own voltage rail.
• Enables extreme asymmetry at runtime:
  • 1 X-core at 3.6 GHz — 1 V
  • 2 mid cores at 1.5 GHz — 0.7 V
  • 4 LITTLE cores at 300 MHz — 0.5 V
• Transitions are ~20-50 µs; Android's EAS scheduler picks appropriate core + freq per task.
• The DSU's shared L3 keeps running at a cluster clock (typically halfway between the fastest and slowest cores).
• Per-core clock gating (ungated during WFI) completes the power toolkit.

• The DSU speaks AMBA 5 CHI on its egress port. Modern phone SoC glue:
  • DSU ↔ NIC-700 (AMBA 5 CHI fabric for phones)
  • Or DSU ↔ CMN mesh (in laptop / automotive SoCs)
• Beyond the DSU, the SoC adds:
  • Memory controller (LPDDR5X, DDR5)
  • GPU (Mali / Immortalis)
  • NPU (Ethos, Apple ANE, etc.)
  • Display / video / ISP / DMA
• CHI gives the DSU uniform coherence semantics — any GPU access can be Stage-2 translated + GP-checked + SLC-cached.
• The ACP (Accelerator Coherency Port) on DSU allows one accelerator to share the cluster's coherence domain — historic legacy, newer designs use CHI / CXS instead.

• Designed for ASIL-B / ASIL-D automotive safety targets.
• Adds:
  • Dual-core lockstep mode (DCLS) — two cores run identical instructions, hardware compares
  • Parity / ECC on internal busses
  • Safety-island monitoring of DSU state
  • Isolation groups within the cluster for freedom-from-interference
• Targets: automotive ADAS (L2+ driver assist) and infotainment SoCs running Android Auto / Linux alongside a safety microcontroller.
• Partners: NVIDIA Drive Thor variants, Mercedes MB.OS, Qualcomm Snapdragon Ride, Renesas R-Car Gen5.

• DSU has its own PMU — independent from the per-core PMUs.
• Events include:
  • L3 reads / writes / hits / misses
  • Snoop filter lookups + invalidations
  • Cache-to-cache transfers
  • Coherent evictions
  • CHI egress bandwidth
• Visible via Linux perf stat -e arm_dsu_0/... on DSU-110/120.
• Essential for debugging whether the L3 hit rate or the inter-core coherence is the bottleneck in a multi-threaded workload.

• L3 slice count (1-4, later 1-8) — trades die area for miss latency
• L3 slice size (512 KB / 1 MB / 2 MB / 4 MB per slice)
• Snoop filter size (typically ~1.5× sum of L2)
• Max supported core count — 4, 8, 12, 14
• Core mix — any mix of X / A-mid / A-LITTLE, each with its own L1/L2
• Number of CHI egress ports — 1 for phones, 2-4 for laptops
• ACP option — whether to include a non-CHI accelerator-coherency port
• Clock / voltage domains — 1 or more per core, 1 for cluster L3

• Cortex-A 06 — Microarchitecture & DynamIQ — DSU from the CPU side, 1+3+4 scheduling
• AMBA 05 — CHI Coherency — the packet-switched protocol DSU egresses
• Neoverse 03 — CMN Mesh — the server-class big-brother fabric
• System IP 04 — MPAM & CoreSight — observing + partitioning across the DSU

• "Why did DynamIQ replace big.LITTLE?" → big.LITTLE had two fixed clusters with CCI-400 between them. DSU is one cluster with up to 14 heterogeneous cores, shared L3, and per-core DVFS — much more flexible.
• "What's inside a DSU?" → SCU + snoop filter + shared L3 (sliced) + coherence crossbar + per-core async bridges + CHI egress.
• "DSU vs CMN?" → DSU is a cluster fabric (up to 14 cores, 32 MB L3). CMN is a system mesh (128+ cores, 512 MB SLC). A laptop SoC may have both; a phone SoC just has a DSU.

• "Why split L3 into slices?" → parallel access (each slice has own tag RAM + arbiter), spreads bandwidth across slices, enables per-slice power gating at idle.
• "What is the ACP?" → Accelerator Coherency Port — a historic non-CHI port for a single attached accelerator to share the cluster's coherence domain. Largely superseded by CHI + CXS in modern designs.
• "Why DSU-120AE?" → automotive (ASIL-B/D) adds dual-core lockstep, parity on internal busses, safety-island monitors. Halves effective core count.