AXI Deep Dive

• AHB couples address and data phases. One slow transaction stalls the entire bus.
• AXI fully decouples five channels, each with its own VALID/READY handshake.
• Transactions carry IDs — the same master can issue multiple outstanding transactions, and the slave (e.g. DRAM controller) can reorder and return them in any order as long as ordering rules per-ID are preserved.
• This is the single most important AMBA innovation since 1996 — it's what lets a modern CPU maintain hundreds of outstanding loads while streaming DMA writes concurrently.

• Source drives VALID and the payload; sink drives READY.
• Transfer happens on the rising ACLK edge when both are asserted.
• Source must not wait for READY before asserting VALID (no combinational dependency) — this prevents deadlock and keeps static timing clean.
• Sink may wait for VALID before asserting READY.
• Once VALID is high, it stays high until the handshake; payload must not change.

// Source side — safe shape
always_ff @(posedge ACLK) begin
  if (!ARESETn) begin
    VALID <= 0;
    data  <= 0;
  end else begin
    if (VALID && READY) begin
      // handshake — advance
      VALID <= next_valid;
      data  <= next_data;
    end else if (!VALID && have_data) begin
      // present new data
      VALID <= 1;
      data  <= new_data;
    end
  end
end

Sink-side back-pressure is just: assert READY whenever it has buffer room.

4 KB rule: a single INCR burst must not cross a 4 KB address boundary — because that's the smallest MMU page size, and bursts that cross pages would risk partial permission violations.

AxSIZE must be ≤ the data-bus width. Narrower bursts on a wide bus waste lanes (write strobes, or read-mask on the consumer side).

• Every transaction carries an AxID (AWID or ARID). Responses come back tagged with the same ID (BID or RID).
• Ordering rules (AXI4):
  • Transactions with the same ID: responses return in order.
  • Transactions with different IDs: responses may return in any order.
• This lets a DRAM controller satisfy ID=7 (which hit a page) before ID=3 (which missed and had to open a new row).
• A master that wants strong ordering just uses one ID; a master that wants bandwidth uses many.

• AXI3 allowed write-data interleaving: a master could send W-beats belonging to two different write IDs alternately on the W channel.
• This was bounded by AWINTERLEAVE depth ≥ 2.
• AXI4 removed it. Write data must now be sent strictly in the order of the AW transactions, and all beats of one AW are sent before the first beat of the next.

Why? Because nobody ever used it. Masters either couldn't buffer the second write's data, or preferred to serialise writes to avoid corner cases. Verification shops hated it — the state space exploded for zero benefit.

• WSTRB[N-1:0] has one bit per byte lane of WDATA. A bit of 1 means "write this byte"; 0 means "ignore it".
• Lets partial writes happen without separate transactions — useful for byte and half-word stores on a 64-bit bus.
• Align strobes with WDATA byte order: for little-endian, bit 0 corresponds to byte 0 (bits 7:0 of WDATA).
• The slave must honour WSTRB exactly — setting it wrong corrupts neighbouring bytes.

• AxCACHE[3:0] tells the bus what memory type the transaction targets. Crucial for cache maintenance and correctness.
• Bits:
  • [0] Bufferable — write buffer allowed to re-order (writes)
  • [1] Cacheable / Modifiable — the transaction can be merged, split, or buffered by the system cache
  • [2] Read-Allocate — cache should allocate on read miss
  • [3] Write-Allocate — cache should allocate on write miss
• AXI4 renamed some bits (Modifiable / Allocate) and clarified semantics for system-cache-aware slaves.

The MMU page table attributes on Armv8 map directly to AxCACHE when the CPU issues the transaction.

• AxPROT[2:0] = 3 attribute bits on every transaction:
  • [0] Privileged — 1 = privileged CPU mode
  • [1] Non-Secure — 1 = NS, 0 = Secure
  • [2] Instruction — 1 = instruction fetch, 0 = data
• Bus filters (TrustZone AXI filters, SMMU fault modes) gate traffic based on AxPROT.
• An AXI5 SoC with RME (Realm Management Extension) adds AxPROT[3]=NSE so a 4-way security state (Root/Realm/Secure/Non-Secure) can be encoded.

AxQOS[3:0] — Quality of Service

• 4-bit hint: higher value = higher priority.
• Implementation-defined — the spec does not dictate behaviour.
• Typical use: memory controllers prioritise display-refresh or real-time DMA over CPU loads.

AxREGION[3:0]

• 4-bit region identifier, set by the interconnect, not the master.
• Lets a slave expose up to 16 distinct logical regions from one physical port.
• E.g. a DRAM controller exposing banked regions without needing 16 separate slave ports.

• Per-channel USER signals (AWUSER, WUSER, BUSER, ARUSER, RUSER) — implementation-defined width, spec-defined presence.
• Intended for SoC-specific sideband: PMU hints, parity, ECC side-channel, IP licensee IDs, SMMU stream hints.
• Master and slave must agree on the semantics — the spec does nothing here except carry bits.
• AMBA5 formalises more attributes so the USER channel isn't the only sideband: AxMMUSID, MPAM PARTID, MTE tags, etc.

• Stripped-down AXI4 for control/status register access:
  • Burst length = 1 (no AxLEN)
  • No AxID (or implied ID=0)
  • No AxLOCK, AxCACHE, AxBURST, AxQOS
  • AxSIZE fixed to bus width
  • WSTRB only for byte-level writes
• Still keeps the five channels and the VALID/READY handshake — so it composes cleanly with full AXI via a gateway.
• Used by virtually every register-mapped IP block a CPU talks to today.

• A pure data pipe. No address, no response. Just data flowing between a Source ("Master") and Sink ("Slave").
• Signals:
  • TDATA — data (any width)
  • TVALID, TREADY — VALID/READY handshake
  • TLAST — end of packet
  • TKEEP — per-byte "this byte is valid"
  • TSTRB — per-byte "this byte is a data byte (vs null)"
  • TID, TDEST, TUSER — routing & metadata
• The de-facto FPGA streaming interface. Every Xilinx video, Ethernet, and DSP IP block exposes it.

Significant additions

• Atomic transactions — AtomicStore, AtomicLoad, AtomicSwap, AtomicCompare — offloaded from the CPU to the memory system (for LSE instructions on Armv8.1+).
• Cache stashing — AxSTASH hints to push data into a target cache (NIC → L3).
• User request attributes — AxNSAID (Non-Secure Access Identifier for RME/CCA).
• MTE (Memory Tagging Extension) support — tag bits on every transfer.
• Deallocation hints — AxCHUNK / WriteNoSnoop / CMO (Cache Maintenance Operations).

• Routes masters to slaves based on AxADDR decoding.
• Each slave port has its own arbiter across masters; each master port has its own response multiplexer across slaves.
• ID re-mapping: the crossbar prepends a master-index to AxID so slaves see unique IDs, and strips it on the way back.
• Typical delays inserted per stage for timing closure — a 4×4 AXI crossbar at 2 GHz typically has 3–5 cycle latency per direction.
• Must preserve ordering per source-ID: the same master's same-ID transactions come back in order.

Pitfall: VALID → READY dependency

Source must not wait for READY before asserting VALID. Creating that combinational loop deadlocks the bus and breaks STA.

Pitfall: Changing payload while VALID is high

Once VALID is asserted, the payload (ADDR, DATA, etc.) must not change until READY takes effect.

Pitfall: RLAST / WLAST missed or premature

RLAST must be high on exactly the last beat. Generating it too early or too late confuses the master's burst counter.

Pitfall: Burst crosses 4 KB boundary

Protocol-illegal. Split at the master or have the slave error out.

Pitfall: Write response before all W-beats

Slave must wait for WLAST before issuing B. Some slaves combine this with an internal write buffer; you still must respect the ordering.

Pitfall: Deadlock rings

If Master A is waiting on Slave X's B channel while A holds up Slave Y's AR queue that X in turn waits on, the bus deadlocks. Topology and depth of outstanding transactions must be analysed.

Pitfall: ID width explosion

Crossbars widen AxID by log2(N_masters). If downstream slaves hard-code the ID width, the crossbar break-out fails.

Pitfall: AxCACHE mismatch vs MMU attributes

CPU's MMU attributes must match what the CPU drives on AxCACHE, or coherency contracts break.

AXI4-Stream loopback — literally wires

No registers at all: just pass VALID/DATA/LAST forward and READY backward. Zero latency, zero area. A perfect DV sanity-check fabric for any Stream DUT.

module axis_loopback #(parameter W = 64) (
  // slave (sink-side) port
  input  logic           s_tvalid,
  output logic           s_tready,
  input  logic [W-1:0]   s_tdata,
  input  logic           s_tlast,
  // master (source-side) port
  output logic           m_tvalid,
  input  logic           m_tready,
  output logic [W-1:0]   m_tdata,
  output logic           m_tlast
);
  assign m_tvalid = s_tvalid;
  assign m_tdata  = s_tdata;
  assign m_tlast  = s_tlast;
  assign s_tready = m_tready;   // back-pressure pass-through
endmodule

Because AXI4-Stream has no address, no ID, and no response channel, a pure combinational pass-through is legal & protocol-compliant.

Single-register pipeline stage (skid buffer)

One flop + one "skid" holding register is the minimum that re-times a VALID/READY channel without breaking the protocol's "VALID must not depend combinationally on READY" rule. Drop into any AXI channel to close timing.

module axi_skid #(parameter W = 32) (
  input  logic         clk, rstn,
  input  logic         s_valid, output logic s_ready,
  input  logic [W-1:0] s_data,
  output logic         m_valid, input  logic m_ready,
  output logic [W-1:0] m_data
);
  logic [W-1:0] skid_q;  logic skid_v;

  always_ff @(posedge clk or negedge rstn)
    if (!rstn) {skid_v, skid_q} <= '0;
    else if (s_valid && s_ready && !m_ready)
           {skid_v, skid_q} <= {1'b1, s_data};
    else if ( m_ready) skid_v <= 1'b0;

  assign m_valid = s_valid | skid_v;
  assign m_data  = skid_v ? skid_q : s_data;
  assign s_ready = !skid_v;
endmodule

This 10-line cell is the backbone of every AXI crossbar, bridge, and clock-domain-crossing FIFO front-end.

module axil_loopback_reg (
  input  logic        ACLK, ARESETn,
  // AW / W / B
  input  logic        AWVALID, input logic [31:0] AWADDR,
  output logic        AWREADY,
  input  logic        WVALID,  input logic [31:0] WDATA,
  input  logic [3:0]  WSTRB,   output logic WREADY,
  output logic        BVALID,  output logic [1:0] BRESP,
  input  logic        BREADY,
  // AR / R
  input  logic        ARVALID, input logic [31:0] ARADDR,
  output logic        ARREADY,
  output logic        RVALID,  output logic [31:0] RDATA,
  output logic [1:0]  RRESP,   input  logic RREADY
);
  logic [31:0] reg_q;
  logic aw_hs, w_hs, b_pend, ar_hs, r_pend;

  // simultaneous AW+W one-beat write handshake
  assign AWREADY =  !b_pend;
  assign WREADY  =  !b_pend;
  assign aw_hs   =  AWVALID && AWREADY;
  assign w_hs    =  WVALID  && WREADY;

  always_ff @(posedge ACLK or negedge ARESETn)
    if (!ARESETn) {reg_q, b_pend, r_pend} <= '0;
    else begin
      // write: byte-strobed update
      if (aw_hs && w_hs) begin
        for (int i = 0; i < 4; i++)
          if (WSTRB[i]) reg_q[i*8 +: 8] <= WDATA[i*8 +: 8];
        b_pend <= 1'b1;
      end else if (BVALID && BREADY) b_pend <= 1'b0;

      // read: one beat
      if (ARVALID && ARREADY) r_pend <= 1'b1;
      else if (RVALID && RREADY) r_pend <= 1'b0;
    end

  assign ARREADY = !r_pend;
  assign BVALID  =  b_pend;  assign BRESP = 2'b00;
  assign RVALID  =  r_pend;  assign RDATA = reg_q;  assign RRESP = 2'b00;
endmodule

• "Why five channels?" → Independent backpressure for AW, W, B, AR, R. Lets the memory controller overlap reads and writes while respecting per-ID ordering.
• "What does AxID buy you?" → Out-of-order responses across IDs; in-order within the same ID. Maps neatly to a CPU's load queue and a DRAM controller's reorder buffer.
• "Why isn't WLAST redundant?" → Because the slave might not know AWLEN in time (gated by arbitration/clock crossings). WLAST is the single bit that authoritatively ends the burst.
• "Why the 4 KB rule?" → Prevents a single burst from spanning two MMU pages with potentially different permissions.

• "What's the difference between AXI4-Lite and APB?" → Channel count (5 vs effectively 2), pipelining, and ecosystem. AXI4-Lite wins on integration, APB wins on area.
• "When do you use AXI4-Stream?" → DSP/video/packet pipelines where there's no address — just a directed flow of data with TLAST packet boundaries.
• "Why did AXI4 drop write interleaving?" → Nobody implemented it usefully; verification was expensive; AXI's response reordering already gave you the bandwidth you wanted.
• "When do you use AXI5 atomics vs Exclusive?" → Atomics for contended counters (faster, one round trip); Exclusive for ABA-style compare-and-swap patterns still supported by older CPUs.