AHB & APB

• Every Cortex-M MCU you touch — STM32, nRF52, LPC, SAM, RP2040 — uses AHB-Lite for the CPU's instruction & data buses and APB for its register-mapped peripherals.
• Cortex-M55 and M85, released in 2020 and 2022, are AHB5-Lite at the core. AHB has outlived AXI by now: it's the low-power bus of record.
• An AHB transaction is one address phase and one data phase. It is the easiest high-speed bus to reason about — especially useful in interviews.
• APB is so simple that a whole UART can live in fewer than 200 lines of Verilog.

// Address phase (driven by master)
HCLK        // single clock
HRESETn     // active-low reset
HADDR [31:0]
HTRANS[1:0] // 00 IDLE, 01 BUSY,
            // 10 NONSEQ, 11 SEQ
HWRITE
HSIZE [2:0] // 001 halfword, 010 word, 011 dword…
HBURST[2:0] // SINGLE, INCR, WRAP4/8/16, INCR4/8/16
HPROT [3:0] // cacheable, bufferable, privileged, D/I
HMASTLOCK

// Data phase (driven by master/slave)
HWDATA[31:0]  // master → slave
HRDATA[31:0]  // slave  → master
HREADY        // slave: xfer complete
HRESP [1:0]   // OKAY, ERROR, RETRY, SPLIT
HSEL_x        // per-slave, decoded from HADDR

• Slave drives HREADY low to extend the current data phase — and by the pipelining rule, that also extends the address phase of the next transfer.
• The selected slave drives HREADYOUT; a global mux ORs all slaves and the bus's overall HREADY comes back to every master.
• Idle slaves must drive HREADYOUT = 1; only the addressed slave may pull it low.
• In AHB-Lite HREADY = HREADYOUT of the selected slave (no arbitration).

AHB-Lite has only OKAY and ERROR — the RETRY / SPLIT machinery was removed as part of the simplification.

• In full AHB, up to 16 masters share the bus via a central arbiter.
• Per-master signals: HBUSREQx, HLOCKx (atomic lock), HGRANTx.
• Arbiter drives HMASTER[3:0] so slaves can identify who's talking (important for SPLIT).
• Policy is implementation-defined — typically round-robin, sometimes fixed priority for real-time masters.
• Masters win the grant one transfer at a time (or one burst at a time if HMASTLOCK asserted).

• Introduced alongside Cortex-M3 in 2004 and formalised in the 2006 AHB-Lite addendum.
• Exactly one master. No arbitration signals, no HMASTER, no HBUSREQ.
• No RETRY / SPLIT — only OKAY and ERROR.
• Perfectly matches an MCU CPU: the Cortex-M has one instruction port and one data port, each an AHB-Lite master talking to a bus matrix.

For multi-master MCU designs, Arm published multi-layer AHB (2002) — a simple interconnect of AHB-Lite masters crossbarred onto AHB slaves. No shared single-master view; each master has its own port into the fabric.

Key additions over AHB-Lite

• HNONSEC — 1 bit: 0 = Secure, 1 = Non-Secure. Aligns AHB with TrustZone for Armv8-M and Armv8-A.
• HEXCL / HEXOKAY — exclusive access support, equivalent of AXI's LDREX/STREX pair.
• HMASTER extended to help the PPC / bus filter identify the originating master for security checks.
• HAUSER / HWUSER / HRUSER — user sideband signals for implementation-specific attributes.
• Optional multi-copy atomicity (MCA) compliance — a system-level guarantee that all observers see writes in the same order.

PCLK                // single clock
PRESETn             // active-low reset
PADDR [31:0]
PSEL_x              // per-slave select
PENABLE             // two-phase indicator
PWRITE
PWDATA[31:0]
PRDATA[31:0]
PREADY              // (APB3+) slave ack
PSLVERR             // (APB3+) error
PPROT [2:0]         // (APB4+) secure/priv/data
PSTRB [3:0]         // (APB4+) byte strobes
PNSE / PWAKEUP      // (APB5) security / wake

• The canonical boundary between the fast AHB system bus and the slow APB peripheral bus is an AHB-to-APB bridge.
• Responsibilities of the bridge:
  • Accept AHB transactions; hold HREADY low until the APB side completes.
  • Drive PSEL / PENABLE according to the two-phase APB protocol.
  • Translate HSIZE / HWRITE / HPROT into PSTRB / PWRITE / PPROT.
  • Map AHB address ranges to PSELx lines (one PSEL per peripheral).
  • Return PSLVERR → HRESP=ERROR cleanly.

• For MCU-class systems that need 2–4 masters (CPU + DMA + USB, say) without the complexity of AXI.
• Each master has its own AHB-Lite port into the fabric — no shared address bus.
• The matrix contains one per-slave arbiter; decoding per-master routes each request to its target slave.
• If two masters target different slaves, they run concurrently with full bandwidth. If they target the same slave, the per-slave arbiter (round-robin or fixed) picks a winner.

Pitfall: forgetting HTRANS gating

A slave that latches HADDR unconditionally will misfire on IDLE / BUSY cycles. Always gate on HSEL && HTRANS[1] && HREADY.

Pitfall: HREADYOUT during idle

Idle slaves must drive HREADYOUT = 1; if a slave tristates or drives 0, the whole bus hangs.

Pitfall: ERROR response timing

AHB mandates a two-cycle ERROR: in the first data cycle drive HRESP=ERROR with HREADY=0, and in the second drive HRESP=ERROR with HREADY=1. Miss this and the master's fault-handler behaves incorrectly.

Pitfall: APB without PREADY timeout

If an APB slave misbehaves and never asserts PREADY, the bridge — and thus the whole AHB above it — stalls indefinitely. Most bridges implement a watchdog that forces PSLVERR on timeout.

Pitfall: Mixed HSIZE on the same burst

All beats in an AHB burst must share HSIZE. A half-word + word burst is protocol-illegal — split into two bursts instead.

Pitfall: WRAP across 1 KB boundary

AHB forbids a burst from crossing a 1 KB boundary. Masters must split longer transfers. Slaves should assert ERROR if they see one anyway.

Minimal APB3 slave — ~15 lines

module apb_loopback_reg (
  input  logic        PCLK, PRESETn,
  input  logic        PSEL, PENABLE, PWRITE,
  input  logic [31:0] PADDR, PWDATA,
  output logic [31:0] PRDATA,
  output logic        PREADY, PSLVERR
);
  logic [31:0] r_q;
  always_ff @(posedge PCLK or negedge PRESETn)
    if (!PRESETn)                          r_q <= 32'h0;
    else if (PSEL && PENABLE && PWRITE)  r_q <= PWDATA;

  assign PRDATA  = r_q;
  assign PREADY  = 1'b1;   // always ready (zero wait states)
  assign PSLVERR = 1'b0;
endmodule

This really is the minimum: one flop, three combinational outputs. PREADY tied high makes every access a two-cycle SETUP/ACCESS round-trip.

Even smaller — APB read-only status register

module apb_status_ro #(parameter W = 32) (
  input  logic        PCLK, PRESETn,
  input  logic        PSEL, PENABLE,
  input  logic [W-1:0] status_i,   // external live signal
  output logic [31:0] PRDATA,
  output logic        PREADY, PSLVERR
);
  assign PRDATA  = {{(32-W){1'b0}}, status_i}; // pure wires
  assign PREADY  = 1'b1;
  assign PSLVERR = 1'b0;
endmodule

For HW bring-up silicon: a mask-ROM'd APB slave often returns a fixed "MAGIC" word so the first boot-check is just if (*APB_BASE == 0xDEADBEEF) go;

• "Why is AHB pipelined?" → To double utilisation of the data bus. Address phase N+1 overlaps data phase N so the bus never idles between transfers.
• "What does HREADY actually do?" → It's the single backpressure signal. Gated by the selected slave, it stretches both address and data phases simultaneously.
• "When would you use WRAP4 vs INCR4?" → WRAP4 for cache-line fills (critical-word-first); INCR4 for linear streaming.
• "Why did AHB-Lite drop SPLIT/RETRY?" → Single-master use case made them unnecessary; the verification cost wasn't worth it.

• "Why two phases on APB?" → Deterministic slave design — one cycle to set up, one cycle to access. Lets you write tiny slaves without FSMs.
• "When do you choose APB over AHB?" → When the peripheral's traffic rate is far below the CPU clock (UART, GPIO, timer) — use APB and save area/power.
• "What does HNONSEC buy you in AHB5?" → Security-attribute propagation — the same TrustZone contract as AXI4's AxPROT[1], so a Non-Secure transaction can be blocked at the bus matrix.
• "Why does the STM32 have APB1 and APB2?" → Two clock domains — APB1 slow (HCLK/4), APB2 faster (HCLK/2). Each has its own bridge.